EP0455803A1 - Non-interlaced interline transfer ccd image sensing device with simplified electrode structure for each pixel - Google Patents
Non-interlaced interline transfer ccd image sensing device with simplified electrode structure for each pixelInfo
- Publication number
- EP0455803A1 EP0455803A1 EP19910901091 EP91901091A EP0455803A1 EP 0455803 A1 EP0455803 A1 EP 0455803A1 EP 19910901091 EP19910901091 EP 19910901091 EP 91901091 A EP91901091 A EP 91901091A EP 0455803 A1 EP0455803 A1 EP 0455803A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- charge
- electrodes
- image sensor
- shift register
- sensor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 108091008695 photoreceptors Proteins 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 4
- 229910016006 MoSi Inorganic materials 0.000 claims description 2
- -1 TaSiv Inorganic materials 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 241000283986 Lepus Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 230000000063 preceeding effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
Definitions
- This invention relates to image sensing devices and, more particularly, to interline transfer type charge coupled imagers with non-interlaced read—out.
- interline transfer type imaging devices photogenerated charge is collected on a photo charge collection site or photoreceptor, such as in a photodiode pn junction or under the gate of a photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit.
- a photo charge collection site or photoreceptor such as in a photodiode pn junction or under the gate of a photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit.
- a charge coupled register In an area array of such photocharge collection sites it is necessary to transfer the collected photocharge, first into a vertical shift register and then to a horizontal shift register, finally, reaching a charge sensitive detector or amplifier.
- FIGS. 1 and 2 alternate rows of photoreceptors are read out in sequence, odd numbered rows being associated with one, so called, field, and even numbered rows associated with a second field.
- a given row of pixels 10 is addressed by application of a voltage to electrodes 20 and 30 which are both connected to the same vertical clock, ⁇ , .
- photocharge is transferred to the buried channel 40 of a vertical CCD shift register.
- This vertical shift register is composed of buried channel 40, electrodes 20 and 30, which are connected to vertical clock ,, and electrodes 50 and 60 which are connected to vertical clock ⁇ 2 - These electrodes are separated from the substrate semiconductor 70 by an insulating layer 80.
- the regions 65 beneath electrodes 30 and 60 are ion implanted to provide a potential energy difference between regions 25 and 26, controlled by the ⁇ -, clock, and between regions 55 and 56, controlled by the ⁇ 2 clock.
- Such a non-interlaced read—out is desirable if the device is to be used in an electronically shuttered mode for still photography.
- a complete vertical CCD shift register cell is required for each row of photodiodes since photocharge from all photodiodes must be transferred into the vertical shift register simultaneously and maintained as separate charge packets throughout transfer to the output amplifier.
- each pixel would need to contain at least four separate CCD electrodes if a similar manufacturing process is to be used and the same number of clocking voltages maintained.
- an interline transfer type area image sensor having an array of columns and rows of separate pixels and wherein charge collected in the pixels of each column is transferred into a vertical two-phase CCD, such CCD shift register comprising a series of overlapping electrodes, with each electrode being formed from a single level of conductor, separate voltage clocks connected to alternate electrodes, adjacent pairs of said electrodes constituting one complete stage of a CCD shift register, each column pixel being associated with one pair of a vertical CCD's electrodes, an ion implanted barrier region being formed under an edge of each electrode, and means for transferring charge from each pixel into a region under one of the corresponding electrodes .
- the present invention employs a two-phase
- CCD shift register which utilizes only one electrode for each clock phase, thus realizing a simplified non-interlaced read—out type device with improved ratio of photosensitive area to total pixel area.
- This is accomplished by providing a vertical CCD shift register with ion implanted transfer barrier regions such that only one layer of gate electrode is required by each phase of the vertical shift register.
- the design requires only two electrodes for each row of imaging sites and such a structure is not as subject to yield limitations due to intralevel short circuits, such as those caused by photomasking imperfections.
- the self-alignment of the transfer barrier region implants assure excellent transfer efficiency in the CCD shift register.
- FIG. 1 is a plan view of a typical prior art interlaced read—out type imaging device
- FIG. 2 is a fragmentary, partially schematic vertical section view through a semiconductor device, taken along the lines A-A of FIG. 1, illustrating a prior art construction
- FIG. 3a through FIG. 3c are partial plan views of various stages during the making of an interline transfer type area image sensor in accordance with the present invention
- FIG. 4a, FIG. 4b and FIG. 4c are fragmentary, partially schematic cross-sectional views taken along the lines A 1 —A 1 , B—B and C—C of FIG. 3c, respectively
- FIG. 5 is a fragmentary, partially schematic cross-section view of an alternative embodiment of the present invention.
- an interline transfer type area image sensor has semiconductor substrate 100 provided with channel stop regions 110 and buried channel regions 120 as shown in plan view in FIG. 3a and in cross-sectional views in FIG. 4.
- the substrate 100 may be a p—well diffused into an n-type silicon wafer.
- An insulating oxide 125 is grown over the semiconductor surface and a single level layer of polysilicon conductor 130 is deposited. Barrier regions are provided in regions 140 by methods such as described by Losee et al in u.S. Patent 4,613,402, and illustrated in FIG. 3b.
- an insulating layer of oxide 135 is grown over the polysilicon conductor 130 and a second barrier region 160 is provided by ion implantation of appropriate dopant atoms.
- a second single level layer of polysilicon conductor is deposited and patterned to form CCD electrodes 170 (see FIG. 4b). Regions 180, which are not covered with the polysilicon conductors, are then implanted with appropriate impurities to form rows and columns of charge collection sites photoreceptors for collection of photogenerated charge.
- FIG. 4a shows a cross section of a row of the interline area image sensor having pixels 180.
- FIG. 4c shows in cross section a column of the interline area image sensor having pixels 180. In this position the layers 170 are directly above layers 130.
- FIG. 4b is a cross section of one of the two-phase vertical CCD shift registers. Separate voltage clocks ⁇ , and 2 are respectively connected to alternating electrodes 130 and 170. As shown, the electrodes 170 overlap electrodes 130. To operate this device a positive going voltage pulse is applied to electrodes 130 which permits photogenerated charge from pixels 180 to transfer to the buried channel 120 beneath electrode 130 via the surface channel gap 191 (see FIG. 3a and FIG. 3b).
- clock voltages ⁇ , and ⁇ are applied to transfer the photocharges to an appropriate charge detection circuit in a well known manner. In this way a non-interlaced read-out of the photogenerated charges is accomplished and each row of pixels 180 is associated with one pair of electrodes 170 and 130.
- a voltage pulse is applied to simultaneously deplete all of the photoreceptor sites of any accumulated signal charge.
- substrate 100 is a p-well diffused into an n—type wafer
- a voltage pulse applied beweeen the p—well and the n—type wafer may be used to deplete the photoreceptor sites.
- photocharges are generated by absorption of incident light.
- all accumulated photoreceptor photocharges are transferred simultaneously into the vertical CCD shift register and read out as described above.
- FIG. 5 An alternative embodiment of this invention is shown schematically in FIG. 5.
- the charge collection regions of the device, 180 are connected to capacitor plates 200 through a conducting pillar 210.
- a conducting pillar may be fabricated as described by -1- Raley et al, J. Electrochemical Soc. 135. 2640 (1988).
- the capacitor plates are covered with a photoconducting layer 220 and top electrode layer 230. Photogenerated charge is transferred across the photoconductive layer and transferred to the charge collecting regions 180. This photocharge is then further transferred from regions 180 to the vertical shift register and read out as described in the preceeding paragraph.
- a third embodiment of the present invention is one where the conductive electrodes 130 and 170 of the figures are composed of composite layers of polysilicon and one or more material selected from the group consisting of WSi , MoSi , TaSi , TiSi , W, Mo, or Ta.
- n—type semiconductor doped to approximately 30 ohm-cm resistivity was provided with a p-type region by implantation of boron atoms with a dose of 1.0E+12 cm*''-2 and diffused to a depth of thickness of approximately 3.5 ⁇ m.
- Channel stop barrier regions are formed by implantation of boron with a dose of 1.0E+13 cm**-2, and subsequently growing an oxide of thickness approximately 4000 A. An additional oxidation and subsequent etch—back reduces this oxide to a thickness of approximately 2500 A.
- a buried channel region is formed by ion implantation of arsenic atoms, with a total dose 6.0E+12 cm**-2, and transfer gate oxide approximately 500 A thick, is grown in the charge transfer region and over the photodiode regions.
- Polysilicon electrodes and edge aligned boron implanted barrier regions were then formed according to procedures described by Losee et al, U.S. Patent 4,613,402, and phosphorus was implanted into the photodiode region with a dose of 4.0E+12 cm**—2.
- a thin oxide layer was grown at a temperature of 950 ⁇ C, in a wet ambient, for approximately 8 minutes.
- An insulating layer was deposited by chemical vapor deposition, consisting of approximately 1000 A undoped oxide covered by 5000 A of oxide doped with approximately 4 wt% boron and 4 wt% phosphorus.
- the device was subsequently annealed in an inert ambient for 30 minutes at a temperature of 900°C, contact openings were etched and an aluminum interconnect pattern was fabricated.
- the pixel dimensions of this device were 9.0 ⁇ m, horizontally, by 9.0 ⁇ m vertically.
- image sensors of the interline transfer type with non-interlaced read-out sequence may be required.
- interline transfer type image sensing devices photogenerated charge is transferred from a pixel into a vertical CCD shift register.
- interlaced read—out sequence alternate rows of pixels comprising one field are read out, one row at a time. Then, the second field, consisting of the remaining alternate rows of pixels, is read out.
- the vertical shift CCD register structure in such a device is composed of two or more overlapping levels of polysilicon electrodes associated with each row of pixels.
- this interlaced read-out is frequently not desirable and a non-interlaced read-out, wherein photogenerated charge from each row is transferred in sequence, is preferred.
- a non-interlaced interline transfer imaging device with simplified structure, and, hence improved manufacturability is described.
- the device utilizes two— hase vertical CCD shift registers with ion implanted barrier regions, which may be self—aligned, such as described by Losee et al U.S. Patent 4,613,402, to produce a device with the minimum number of two polysilicon electrodes associated with each pixel.
- the device also provides improved topography for application of integral color filter arrays and maximizes the photosensitive area.
Abstract
L'invention concerne un capteur d'images du type à transfert d'interlignes, qui fonctionne en mode non entrelacé et possède un réseau de colonnes et de rangées de photorécepteurs dans lesquelles la charge provenant de chaque pixel est transférée vers un étage d'un registre vertical CCD à décalage à deux phases, constitué par des électrodes adjacentes du dispositif CCD. Chaque électrode d'un étage possède une horloge de tension individuelle. Une zone barrière d'implantation ionique est prévue sous un des rebords de chaque électrode.The invention relates to a line transfer type image sensor, which operates in non-interlaced mode and has an array of columns and rows of photoreceptors in which the charge from each pixel is transferred to a stage of a two-phase shift CCD vertical register, consisting of adjacent electrodes of the CCD device. Each electrode of a stage has an individual voltage clock. An ion implantation barrier zone is provided under one of the edges of each electrode.
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US44353689A | 1989-11-29 | 1989-11-29 | |
US443536 | 1989-11-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0455803A1 true EP0455803A1 (en) | 1991-11-13 |
Family
ID=23761178
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19910901091 Withdrawn EP0455803A1 (en) | 1989-11-29 | 1990-11-28 | Non-interlaced interline transfer ccd image sensing device with simplified electrode structure for each pixel |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0455803A1 (en) |
JP (1) | JP3100624B2 (en) |
WO (1) | WO1991008590A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5111263A (en) * | 1991-02-08 | 1992-05-05 | Eastman Kodak Company | Charge-coupled device (CCD) image sensor operable in either interlace or non-interlace mode |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6033345B2 (en) * | 1979-06-08 | 1985-08-02 | 日本電気株式会社 | Charge transfer imaging device and its driving method |
JPS5875382A (en) * | 1981-07-20 | 1983-05-07 | Sony Corp | Solid-state image pickup device |
JPH0754973B2 (en) * | 1985-01-14 | 1995-06-07 | 株式会社東芝 | Driving method for solid-state imaging device |
US4875100A (en) * | 1986-10-23 | 1989-10-17 | Sony Corporation | Electronic shutter for a CCD image sensor |
US4908518A (en) * | 1989-02-10 | 1990-03-13 | Eastman Kodak Company | Interline transfer CCD image sensing device with electrode structure for each pixel |
-
1990
- 1990-11-28 WO PCT/US1990/006819 patent/WO1991008590A1/en not_active Application Discontinuation
- 1990-11-28 EP EP19910901091 patent/EP0455803A1/en not_active Withdrawn
- 1990-11-28 JP JP03501510A patent/JP3100624B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
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See references of WO9108590A1 * |
Also Published As
Publication number | Publication date |
---|---|
JP3100624B2 (en) | 2000-10-16 |
JPH05502757A (en) | 1993-05-13 |
WO1991008590A1 (en) | 1991-06-13 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: STEVENS, ERIC, G. EASTMAN KODAK COMPANY Inventor name: TREDWELL, TIMOTHY, JOHN Inventor name: LOSEE, DAVID, L. Inventor name: NELSON, EDWARD, T. |
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17P | Request for examination filed |
Effective date: 19911115 |
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17Q | First examination report despatched |
Effective date: 19931125 |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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18D | Application deemed to be withdrawn |
Effective date: 19970402 |