JP3590944B2 - Charge-coupled semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a charge-coupled semiconductor device, and more particularly to a charge-coupled or transfer element called a CCD (Charge Coupled Device).
[0002]
[Prior art]
The CCD transfers a carrier generated by light incident on a light receiving portion by a clock pulse applied to a transfer electrode and extracts the carrier as a video signal. Various driving methods are known as the transfer method. Such a driving method includes a two-phase driving method, and a single-phase driving method capable of transferring charges by a single electrode is excellent in terms of a circuit configuration and controllability.
[0003]
As a charge transfer device, a buried channel type CCD is known, in which movable charges are accumulated and transferred in an induction channel in a semiconductor layer. In a general surface moving CCD, a trapping effect occurs at an interface between a surface oxide film and a silicon substrate. In a buried channel CCD, this trapping effect can be prevented, so that charge transfer efficiency is improved. In addition, since carrier scattering at the interface is eliminated, charge transfer efficiency can be improved. As a result, operation at a high frequency can be realized.
[0004]
In particular, an inversion layer is formed on a part of the semiconductor surface of each light receiving cell, and this inversion layer acts as a virtual electrode (virtual electrode or virtual electrode), thereby protecting the cell region from gate-induced potential change. The buried channel type single-phase driving CCD is effective.
[0005]
FIG. 11 schematically shows an example of a frame transfer (FT) type virtual phase CCD incorporating such a virtual electrode. The CCD has a light receiving unit (imaging unit) 1 and a storage unit (memory unit) 2 and transfers electrons photoelectrically converted according to the amount of light incident on a light receiving cell of the light receiving unit 1. In step S2, the data is temporarily stored, and output by the register 3 via the output amplifier 4.
[0006]
In the light receiving section 1, in each of the N ⁻ type channel regions 4 separated by the channel stopper region 3 (shown as adjacent channel regions 4a and 4b for understanding in the drawings), the charge transfer direction is substantially orthogonal. A large number of polysilicon transfer gates 5 are intermittently arranged at a predetermined pitch, and inversion layers 9a and 9b as virtual electrodes are formed between the transfer gates by impurity doping. The accumulating portion 2 is separated into respective channel regions 7a and 7b by corresponding channel stopper regions 6 so as to receive the transfer charge from the light receiving portion 1, and the polysilicon transfer gates 8 are intermittently arranged at a predetermined pitch. I have.
[0007]
FIG. 12 schematically shows a cross section (cross section taken along the line XII-XII in FIG. 11) of the light receiving unit 1. For example, the SiO ₂ film 10 is formed on the surface of the N ⁻ type semiconductor layer 13 and the above-described transfer is performed. gate 5 is enabled to transfer the charges in the substrate (optical carrier) by the clock pulses phi ₁ and provided at a predetermined pitch. A P ⁺ -type inversion layer 9b is formed as a virtual electrode between the transfer gates 5 by doping with boron or the like, and the buried channel immediately below the P ⁺ -type inversion layer 9b. Note that + in the figure is an implanted ion (implanted donor).
[0008]
When explaining the operation principle of the light receiving portion 1, the inversion layer 9b, with the cell portion from the potential change due to gate induced is protected, by applying a clock signal phi ₁ to the gate 5 of the single-phase electrodes, the gate The potential maximum values in the regions I and II below the region 5 repeatedly increase and decrease based on the fixed potential maximum values in the regions III and IV below the inversion layer 9b. Potential Then, two gate states (phi ₁ high, low) higher than the potential maximum area I region II in, also, since the region IV is maintained at a high potential than the region III, by switching the phi ₁ Are alternately changed as shown by a solid line and a dashed line, and the directionality of charge transfer for transferring charges (electrons) in the X direction is obtained.
[0009]
In the light receiving section 1, in each light receiving cell 11 between the channel stopper regions 3-3, an AB drain 12 (Anti-Blooming (AB) having a function of sucking up excess charge so that generated charge larger than the capacity does not leak to an adjacent cell. AB) drain) is formed.
[0010]
When a single pixel structure of a CCD is classified, a horizontal overflow drain type (LOD) having a discharge port on a plane as shown in FIGS. And a vertical overflow drain type (VOD) for extracting excess charges in the direction of the substrate as shown in FIG.
[0011]
According to the horizontal overflow drain type shown in FIGS. 13 to 15, as shown in FIGS. 11 and 12, in the light receiving section 1, the charge transfer direction of each of the channel regions 4 a and 4 b separated by the channel stopper region 3 is determined. A number of substantially orthogonal polysilicon transfer gates 5 are intermittently arranged at a predetermined pitch, and inversion layers 9a and 9b as virtual electrodes are formed between the transfer gates by impurity doping. The aperture ratio of the light receiving unit 1 is, for example, about 85%.
[0012]
That is, an SiO ₂ film 10 is formed on the surface of an N ⁻ type semiconductor layer (well) 13 formed on a P ⁻ type silicon substrate 14, and the above-mentioned transfer gates 5 are provided at a predetermined pitch on the SiO ₂ film 10. and to be able to transfer the charges in the substrate (optical carrier) by phi _1. P ⁺ -type inversion layers 9 a and 9 b are formed as virtual electrodes between the transfer gates 5 by doping with phosphorus or the like, and the buried channel immediately below the P ⁺ -type inversion layers 9 a and 9 b. The operating principle of the light receiving unit 1 is the same as that described with reference to FIG.
[0013]
Then, in order to control the surplus charge in the light receiving cell, an AB including an N ⁺ type drain region 15 and a P ⁻ type potential barrier region 16 surrounding the drain region in the N ⁻ type semiconductor layer 13 between adjacent cells. The drain 12 is formed in contact with the channel stopper region 3A on both sides. A polysilicon gate 18 is attached to the drain region 15 of the AB drain 12 via a contact hole 17, a voltage is applied from a metal electrode 21 via a via hole 20 in an insulating layer 19, and a predetermined potential barrier potential is applied. To produce
[0014]
That is, a predetermined voltage is applied from the electrode 21 to the gate 18 to make the N ⁺ -type drain region 15 the same potential as the gate 18, and the potential of the P ⁻ -type potential barrier region 16 is adjusted by this potential. 4b, a surplus charge 30 exceeding a potential barrier formed near the PN junction 22 is absorbed by the N ⁺ -type drain region 15 and discharged through the gate 18 and the electrode 21.
[0015]
However, in this horizontal overflow drain type structure, the drain region 15 for absorbing the surplus charge has a function of absorbing the charge. Therefore, when the CCD is used as the light receiving element, the drain region 15 (and the gate 18) is used. ) Does not function as a light receiving unit and is a dead area. Therefore, the aperture ratio of the light receiving section is only about 85%, which is not enough.
[0016]
Also, when used as an analog memory, the drain region 15 does not function as a charge storage region, and thus the basic characteristics (dynamic range) of the CCD are insufficient for the high necessity.
[0017]
On the other hand, according to the vertical overflow drain type shown in FIG. 16, a P-type well 32 is formed in an N-type silicon substrate 31, and within this P-type well, an N ⁺ -type impurity diffusion region 33 and further a P ⁺ -type impurity are formed. A diffusion region 36 is formed, a photodiode PD formed by a PN junction (J) forms a photosensitive region 38 (pixel), and a P ⁺ -type impurity diffusion region 37 and an N-type impurity diffusion region 34 are shown in FIG. A vertical register 48 corresponding to the storage unit 2 is formed in a cell.
[0018]
The carriers generated in the photosensitive region 38 are sent to a vertical register 48 via a read channel 47 and stored therein. The cell having the photosensitive region 38 and the register 48 is separated from an adjacent cell by a P ⁺ type channel stopper region 35. On the surface side, a Si ₃ N ₄ layer 40 and a SiO ₂ layer 41 are laminated on a SiO ₂ layer 39 as a gate insulating film 42, a transfer electrode 43 serving as a gate of a register is provided, and an interlayer insulating film 44 is formed. A light-shielding layer 45 is formed with the interposition. Further, the photosensitive region 38 is covered with the above-mentioned interlayer insulating film 44.
[0019]
A potential barrier for absorbing the surplus charge in the light receiving cell is formed in a region 38 directly below the N ⁺ type region 33, which is controlled by the potential of the substrate 31 (substrate potential). It is absorbed in the direction of 31.
[0020]
However, in the case of the vertical overflow drain type, the aperture ratio of the cell is only about 15 to 30% due to the presence of the light shielding layer 45, and a microlens (not shown) is used to improve this. In addition to the need to collect incident light (however, there is no need to provide a memory unit (accumulation unit 2 shown in FIG. 11), so the CCD element size is reduced), and the substrate area below the area 38 is insensitive. Because of the region, the infrared sensitivity is extremely reduced. Therefore, although suitable for color imaging, infrared light including near-infrared light cannot be used as incident light and is unsuitable for use in infrared sensors.
[0021]
In addition, since the thickness or depth of the barrier region 38 is limited, the capacitance determined in the depth direction is limited, and the capacitance is reduced. In this case, the dynamic range is narrowed, and the electric charge is easily leaked to the adjacent cells, so that the imaging performance is deteriorated.
[0022]
[Problems to be solved by the invention]
An object of the present invention is to improve the quantum efficiency by effectively expanding the light receiving area and securing infrared sensitivity, to improve the dynamic range by increasing the capacity, and to cope with the downsizing of the element. An object of the present invention is to provide a charge-coupled semiconductor device.
[0023]
That is, the present invention provides a semiconductor substrate of a first conductivity type, a well region of a second conductivity type formed on the semiconductor substrate, and a plurality of channel regions formed in the well region. A plurality of first conductivity-type channel stopper regions formed at predetermined intervals so as to reach the semiconductor substrate from the surface; and a plurality of channel stopper regions formed adjacent to the channel stopper region in a surface layer portion of the channel stopper region. First and second potential barrier regions of a first conductivity type, and a second potential barrier region formed on the surfaces of the first and second potential barrier regions, the second potential barrier region absorbing excess charges in the channel region. The present invention relates to a charge-coupled semiconductor device having a drain region made of conductive polysilicon .
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
In the charge-coupled semiconductor device according to the present invention, a first conductive type first channel region (for example, an N ⁻ type channel region 64a described later; the same applies hereinafter) as the channel region and a first conductive type second channel region are used. (For example, an N ⁻ type channel region 64b described below: the same applies hereinafter) and a second conductivity type isolation region (for example, a P ⁺ type channel stopper region 63A described below: the same applies hereinafter). , Each potential barrier region is formed in the first and second channel regions, and an excess charge absorption layer is formed in contact with the surfaces of the isolation region and each potential barrier region.
[0025]
Also, a plurality of charge transfer electrodes (for example, a polysilicon gate 5 described later; the same applies hereinafter) are intermittently arranged in the charge transfer direction of the channel region, and a potential distribution fixing channel is provided in the channel region between these charge transfer electrodes. A semiconductor region of the second conductivity type (for example, P ⁺ -type inversion layers 69a, 69b or a virtual electrode, which will be described later; the same applies hereinafter) is preferably formed. It is desirable to form between the region and the channel stopper region of the second conductivity type.
[0026]
Further, the first channel region of the first conductivity type and the second channel region of the first conductivity type are separated from each other by the channel stopper region of the second conductivity type, and in the charge transfer direction of the channel region. A plurality of the charge transfer electrodes are intermittently arranged, and the second conductivity type semiconductor region for fixing the potential distribution is formed in a channel region between the charge transfer electrodes, and the semiconductor region is in contact with a surface of the semiconductor region. An excess charge absorbing layer may be formed.
[0027]
Then, the potential barrier region and the surplus charge absorbing layer are formed in a light receiving section (for example, a light receiving section including a light receiving cell 71 described later; the same applies hereinafter), and a charge storage section (for example, FIG. The indicated storage unit 2) may be provided.
[0030]
Specifically, the charge-coupled semiconductor device of the present invention is configured such that the height of the potential barrier in the potential barrier region is controlled by the voltage applied to the surplus charge absorbing layer, and the surplus charge in the cell can be efficiently absorbed. I do.
[0031]
In this case, if the surplus charge absorbing layer is made of an incident light transmitting material, incident light can efficiently enter the cell through the surplus charge absorbing layer.
[0032]
【Example】
Hereinafter, the present invention will be described in more detail with reference to Examples.
[0033]
FIGS. 1 to 8 show a first embodiment in which the present invention is applied to a frame transfer type virtual phase CCD (however, common parts to those of the conventional example shown in FIGS. 11 to 15 are denoted by common reference numerals). And description thereof may be omitted).
[0034]
The basic layout of the CCD according to this embodiment is the same as that shown in FIG. 11, but as shown in FIGS. 1 to 3, each N ^- type channel region separated by a channel stopper region 63 in the light receiving section. A large number of polysilicon transfer gates 5 substantially orthogonal to the charge transfer directions of 64a and 64b are intermittently arranged at a predetermined pitch, and the inversion layers 69a and 69b as virtual electrodes are formed between the transfer gates by impurity doping. I have.
[0035]
These inversion layers 69a and 69b are formed as P ⁺ -type virtual electrodes by doping with boron or the like, and immediately below the inversion layers are the buried channels. The operation principle of the light receiving unit is the same as that described with reference to FIG.
[0036]
Then, in order to control surplus charges in the light receiving cells, adjacent cells are completely separated from each other by the P ⁺ type channel stopper region 63A (that is, the channel stopper region 3A in FIG. 13 is extended). ), this on both sides of the channel stopper region 63A P ^- is type potential barrier region 76 are formed respectively, the N ⁺ -type polysilicon drain layer 75 of the contact hole 77 thereon in contact with the surface of these areas 76 and 63A An AB drain 72 is formed through the gate and absorbs excess charges. A voltage is applied to the drain layer 75 of the AB drain 72 from the electrode 81 via the via hole 80 of the insulating layer 19, and a predetermined potential barrier potential is generated.
[0037]
That is, when a predetermined voltage is applied from the electrode 81 to the drain layer 75, the potential causes the potential between the drain layer 75 and the vicinity of the PN junction (potential barrier 82) between the potential barrier region 76 and the well 73 and the well 73 as shown in FIG. A potential as shown in (a) is formed, and the surplus electric charges 60 in the well 73 are absorbed into the drain layer 75 over the potential barrier 82. Then, the absorbed charge is released through the electrode 81.
[0038]
In addition, the adjacent cells 71-71 are completely insulated and separated by the potential barrier by the channel stopper region 63A, so that no charge leaks. Even if there is a charge that attempts to cross the potential barrier, the charge is absorbed from the channel stopper region 63A into the drain layer 75 and does not invade an adjacent cell.
[0039]
In the above cell configuration, the size of each cell is 6 to 7 μm × 6 to 7 μm in the area of the virtual electrodes 69 a and 69 b, the width w ₁ of the channel stopper area 63 A is about 0.8 μm, and the width of the potential barrier area 76. w ₂ may be about 0.5 μm, and the width w ₃ of the drain layer 75 may be about ₃ μm. As for the impurity concentration, the channel stopper region 63A may have a density of about 10 ¹⁷ / cm ³ , the potential barrier region 76 may have a density of about 10 ¹⁶ / cm ³ , and the drain layer 75 may have a density of about 10 ²⁰ / cm ³ .
[0040]
In order to fabricate the light receiving portion of the CCD of this embodiment, first, as shown in FIG. 5, an N ^- type well 73 is formed on a P ^- type silicon substrate 14 by a diffusion method, and then, as shown in FIG. Then, the P ⁺ type inversion layers 69a and 69b and the P ⁻ type semiconductor region 76 are selectively formed using a mask (not shown).
[0041]
Next, as shown in FIG. 7, deep impurity diffusion is performed by using the SiO ₂ layer 90 as a mask to form P ⁺ -type channel stopper regions 63 and 63A, and the P ⁻ -type semiconductor region 76 is divided on both sides by the channel stopper region 63A. , Each as a potential barrier region.
[0042]
Next, as shown in FIG. 8, a gate oxide film 10 is formed on the surface, an opening 77 is selectively formed over the channel stopper region 63A and the potential barrier region 76, and then a CVD (Chemical Vapor) is formed. Phosphorus-doped polysilicon is deposited by a Deposition method, and is etched by a photolithography technique to deposit an N ⁺ type polysilicon barrier layer 75 in an opening (contact hole) 77.
[0043]
Thereafter, as shown in FIG. 2, a SiO ₂ layer 19 is deposited on the entire surface by a CVD method, a via hole 80 is formed on the SiO ₂ layer 19 by a photolithography technique, and a metal electrode 81 is selectively deposited.
[0044]
The CCD according to the present embodiment is different from the horizontal overflow drain type structure shown in FIGS. 13 to 15 in that the drain layer 75 made of N ⁺ -type polysilicon as a surplus charge absorption layer of the AB drain 72 is formed in the well 73. Since it is formed on the surface, that is, on the surface of the channel stopper region 63A and the surface of the potential barrier region 76, surplus charges in the well 73 are discharged to the upper drain layer 75 beyond the potential barrier determined by the potential barrier region 76. Will be.
[0045]
The height of the potential barrier is controlled by the voltage applied to the polysilicon layer 75, so that excess charges can be effectively absorbed and removed, and the drain layer is not provided in the well 73. In order to transmit the incident light, the lower part of the polysilicon layer 75 also functions as a part of the light receiving part of the normal CCD. Therefore, the above-mentioned dead area can be completely removed from the light receiving element, and the aperture ratio is improved to almost 100%. When the aperture ratio is the same, the cell size can be reduced and the size can be reduced as compared with the conventional structure. The electrode 81 is also made of a material that transmits incident light, for example, polysilicon or ITO (Indium Tin Oxide).
[0046]
As described above, since the drain layer 75 is provided apart from the channel regions 64a and 64b (well 73), the area efficiency of the CCD at the time of receiving light is remarkably improved. The specific effects are summarized below.
[0047]
(1) By increasing the light receiving region, the quantum efficiency of photoelectric conversion of incident light is improved, and infrared sensitivity can be secured.
[0048]
(2) Since the aperture ratio is improved, the size of the element can be reduced.
[0049]
(3) Since charges can be generated by incident light not only in the well 73 but also in the P ⁻ type region 76, the well capacity is increased and the dynamic range of the CCD is improved.
[0050]
(4) In addition to the increase in the well capacity, adjacent cells are completely separated by the channel stopper region 63A, and the drain layer 75 is formed in contact with the channel stopper region 63A. There is no leakage, and good CCD performance can be maintained.
[0051]
(5) Although the drain layer 75 is formed of polysilicon, since such a drain layer is used for a CCD, quality such as crystallinity is not required. There is no problem at all, and it is rather preferable considering its optical transparency and film formability.
[0052]
(6) Further, as can be understood from the above-described manufacturing process, the manufacturing process is very similar to the current process, so that there is no need for a large change in the process or special materials, and the process can be performed simply and at low cost. can do.
[0053]
FIG. 9 shows a second embodiment in which the present invention is applied to a frame transfer type virtual phase CCD.
[0054]
According to this embodiment, as compared with the structure shown in FIG. 1, the drain layers 75a and 75b of N ⁺ type polysilicon are in contact with the surfaces of the P ⁺ type inversion layers 69a and 69b which also function as potential barrier regions. The difference is that it is formed directly on the lever. However, portions corresponding to those in FIG. 1 are given common numbers a and b according to the inversion layers 69a and 69b, respectively.
[0055]
As described above, even if the drain layers 75a and 75b are provided independently in each cell, the surplus electric charges 60a and 60b in each cell are generated by the inversion layers 69a and 69b-well 73 by the voltage applied to the drain layers 75a and 75b. Since it is absorbed and removed by the drain layers 75a and 75b across the potential barrier therebetween, the same effect as in the first embodiment can be obtained. Since the P ⁻ type region 76 is not provided, the cell size can be further reduced.
[0056]
FIG. 10 shows a third embodiment in which the present invention is applied to a CCD having a cell structure similar to that of the conventional example of FIG.
[0057]
In this embodiment, portions common to those in the conventional example of FIG. 16 are denoted by common reference numerals and description thereof is omitted. However, a significantly different configuration is that a potential barrier region in the N ⁺ type region 33 on the light receiving side is used. In contact with the surface of the P ⁺⁺ type region 36, an N ⁺ type polysilicon layer 95 is deposited as a surplus charge drain layer via the contact hole 97 of the interlayer insulating film 44. That is, an electrode 91 that transmits incident light is attached via the via hole 101.
[0058]
Therefore, the surplus charge 50A generated in the well 32 is sucked into the drain layer 95, absorbed and removed. As a result, it is possible to eliminate the insensitive region that lowers the infrared sensitivity as described with reference to FIG. 16, and thus it is possible to improve the infrared sensitivity. Moreover, since the excess charge can be effectively absorbed, the thickness of the well 32 can be increased, the capacity in the substrate depth direction can be increased, and the leakage of the charge to the adjacent cell can be reduced.
[0059]
As described above, the present invention has been described with respect to the embodiment. However, the above-described embodiment can be variously modified based on the technical idea of the present invention.
[0060]
For example, the cross-sectional shape, planar pattern shape, position, and size of the above-described channel stopper region, potential barrier region, drain layer, and the like may be variously changed, and polysilicon is suitable as the material of the drain layer. And other light-transmitting materials.
[0061]
Further, as the above-mentioned AB drain, a horizontal overflow drain type, a surface recombination type (EHR), or the like can be used. Further, it is possible to convert the conductivity type of each semiconductor region constituting the above-mentioned CCD into the opposite conductivity type.
[0062]
The present invention can also be applied to optical devices such as the above-described CCD and photoelectric conversion elements.
[0063]
【The invention's effect】
As described above, according to the charge-coupled semiconductor device of the present invention, it is possible to realize an enlarged light receiving area, an improved aperture ratio, a smaller element, and an improved dynamic range.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view (a cross-sectional view taken along line II of FIG. 2) of a main part of a light receiving unit of a CCD according to a first embodiment of the present invention and an enlarged view of a part thereof.
FIG. 2 is a plan view of a main part of the light receiving unit.
FIG. 3 is a sectional view taken along line III-III in FIG. 2;
4A is a diagram showing a potential distribution curve along (A ′)-(A ″)-(A) in FIG. 2, and FIG. 4B is a diagram showing a potential distribution curve along (B ′)-(B ″)-(B) in FIG. FIG. 4 is a potential distribution curve diagram along ().
FIG. 5 is a cross-sectional view of a main part showing one stage of a manufacturing process of the light receiving unit.
FIG. 6 is a sectional view of a main part showing another stage of the manufacturing process.
FIG. 7 is a cross-sectional view of a main part showing another stage of the manufacturing process.
FIG. 8 is a cross-sectional view of a main part showing still another stage of the manufacturing process.
FIG. 9 is a sectional view of a main part of a light receiving section of a CCD according to a second embodiment of the present invention.
FIG. 10 is a sectional view of a main part of a CCD according to a third embodiment of the present invention.
FIG. 11 is a schematic plan view and a photoelectric conversion characteristic diagram of a conventional CCD and its main part.
FIG. 12 is an operation principle diagram of a light receiving section in the CCD.
FIG. 13 is a plan view of a main part of a light receiving section of the CCD.
14 is a sectional view taken along the line XIV-XIV in FIG.
FIG. 15 is a sectional view taken along the line XV-XV in FIG.
FIG. 16 is a sectional view of a main part of a CCD according to another conventional example.
[Explanation of symbols]
5 Transfer gate 14 Silicon substrate 60 Surplus charges 63 and 63A Channel stopper regions 64a and 64b Channel regions 69a and 69b Inversion layer (virtual electrode)
71 light receiving cell 72 AB drain 73 well 75 drain layer 76 potential barrier region 78 drain layer (N ⁺ type polysilicon layer)
81 ... electrode 82 ... potential barrier

Claims (6)

A first conductivity type semiconductor substrate;
A second conductivity type well region formed on the semiconductor substrate;
A plurality of channel stopper regions of a first conductivity type formed at predetermined intervals so as to reach the semiconductor substrate from the surface of the well region to form a plurality of channel regions in the well region;
First and second potential barrier regions of the first conductivity type formed adjacent to the channel stopper region in a surface layer of the channel stopper region;
And a drain region formed on the surfaces of the first and second potential barrier regions and formed of polysilicon of a second conductivity type for absorbing excess charges in the channel region. Type semiconductor device. 2. The charge-coupled semiconductor device according to claim 1, further comprising a plurality of charge transfer electrodes formed intermittently in a charge transfer direction of the channel region. 3. The charge-coupled semiconductor device according to claim 2, further comprising a semiconductor region of a first conductivity type for fixing a potential distribution formed in a surface portion of a channel region between the charge transfer electrodes . 4. The charge-coupled semiconductor device according to claim 1, wherein the potential of said potential barrier region is controlled by a voltage applied to said drain region. 5. The charge-coupled semiconductor device according to claim 1, wherein said potential barrier region functions as a part of a light receiving section. 6. The charge-coupled semiconductor device according to claim 1, wherein said channel stopper region has a higher impurity concentration than said potential barrier region.

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