JPH09232558A - Charge coupled semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively expand a light receiving region, to secure infrared ray sensitivity, to improve quantum efficiency, to improve dynamic range by increasing capacitance, and to provide a charge coupled semiconductor device which can be corresponded to miniaturization of an element. SOLUTION: N<-> type channel regions 64a and 64b are separated with each other by a P<+> type channel stopper region 63A, a P<-> type potential barrier region 76 is formed on the channel regions 64a and 64b in such a manner that they come in contact with both sides of the channel stopper region 63A, and N<+> type polisilicon layer 75 is formed as an excess charge absorbing layer, in such a manner that it comes in contact with the surface of the channel stopper region 63A and each potential barrier region 76.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupled semiconductor device, and more particularly to a charge coupled or transfer device called CCD (Charge Coupled Device).

[0002]

2. Description of the Related Art A CCD transfers a carrier generated by light incident on a light receiving portion with a clock pulse applied to a transfer electrode and takes out this as a video signal, and various transfer methods are available. Are known. There is a two-phase driving method as such a driving method, but the single-phase driving method capable of transferring charges by a single electrode is excellent in terms of circuit configuration and controllability thereof.

A buried channel type CCD is known as a charge transfer element, which stores and transfers movable charges in an induction channel in a semiconductor layer. In a general surface movement type CCD, a trapping effect occurs at the interface between the surface oxide film and the silicon substrate, but in the buried channel type CCD, this trapping effect can be prevented, so that the charge transfer efficiency is improved.
Further, since carrier scattering at the interface is eliminated, charge transfer efficiency is also improved. As a result, operation at a high frequency can be realized.

Particularly, an inversion layer is formed on a part of the semiconductor surface of each light receiving cell, and this inversion layer is, so to speak, a virtual electrode (v
A buried channel type single-phase drive type CCD, which is designed to protect the cell region from gate-induced potential change by acting as an irtual electrode (virtual electrode or effective electrode), is effective.

FIG. 11 schematically shows an example of a frame transfer (FT) type virtual phase CCD incorporating such a virtual electrode. This CCD
Has a light receiving unit (imaging unit) 1 and a storage unit (memory unit) 2, transfers electrons photoelectrically converted according to the amount of light incident on the light receiving cells of the light receiving unit 1, and the storage unit 2 It is once accumulated and output by the register 3 via the output amplifier 4.

In the light receiving portion 1, each N ^-- type channel region 4 separated by the channel stopper region 3 (adjacent channel regions 4a and 4b are shown for understanding in the drawing).
As shown. ), A large number of polysilicon transfer gates 5 which are substantially orthogonal to the charge transfer direction are intermittently arranged at a predetermined pitch, and inversion layers 9a and 9b as virtual electrodes are formed by impurity doping between the transfer gates. . The storage section 2 is divided into respective channel areas 7a and 7b by corresponding channel stopper areas 6 in order to receive the transfer charges from the light receiving section 1, and the polysilicon transfer gates 8 are intermittently arranged at a predetermined pitch. There is.

FIG. 12 shows a cross section of the light receiving portion 1 (XII--
XII line cross section) is schematically shown, for example, N ⁻ type semiconductor layer 13
A SiO ₂ film 10 is formed on the surface of the substrate, and the above-mentioned transfer gates 5 are provided on the surface of the substrate at a predetermined pitch so that charges (optical carriers) in the substrate can be transferred by a clock pulse φ ₁ . Further, a P ⁺ type inversion layer 9b is formed as a virtual electrode between the transfer gates 5 by doping with boron or the like, and the buried channel is formed immediately below the virtual electrode. In addition, + in the figure is an implanted ion (implanted donor).

The operation principle of the light receiving portion 1 will be described. The inversion layer 9b protects the cell portion from potential change due to gate induction, and applies the clock signal φ ₁ to the gate 5 as a single-phase electrode. Therefore, the maximum potential of the regions I and II under the gate 5 is
The regions III and IV below the inversion layer 9b are repeatedly moved up and down with reference to the fixed maximum potential value. Potential Then, two gate states (phi ₁ high, low) higher than the potential maximum area I region II in, also, since the region IV is maintained at a high potential than the region III, by switching the phi ₁ Are alternately changed as indicated by a solid line and a broken line, and the directionality of charge transfer for transferring charges (electrons) in the X direction can be obtained.

In the light receiving portion 1, the channel stopper region 3-
In each of the light receiving cells 11 between 3 and 3, the AB drain 12 (Anti-Blooming (A
B) Drain) is formed.

When classifying the single pixel structure of the CCD, generally, due to the difference in the method of rejecting the excess charge,
As shown in FIG. 13 to FIG. 15, it is roughly classified into a horizontal overflow drain type (LOD) that has a discharge port on a plane and a vertical overflow drain type (VOD) that drains excess charges toward the substrate as shown in FIG. To be done.

According to the lateral overflow drain type shown in FIGS. 13 to 15, as shown in FIGS. 11 and 12, the charges of the respective channel regions 4a and 4b separated by the channel stopper region 3 in the light receiving portion 1 are charged. A large number of polysilicon transfer gates 5 substantially orthogonal to the transfer direction are intermittently arranged at a predetermined pitch, and inversion layers 9a and 9b as virtual electrodes are formed by impurity doping between the transfer gates.
It has become. The aperture ratio of the light receiving unit 1 is, for example, about 85%.

That is, the SiO ₂ film 10 is formed on the surface of the N ⁻ type semiconductor layer (well) 13 formed on the P ⁻ type silicon substrate 14, and the transfer gates 5 are provided on the SiO ₂ film 10 at a predetermined pitch. The electric charge (optical carrier) in the substrate can be transferred by the clock pulse φ ₁ . Also,
P ⁺ is formed between the transfer gates 5 by doping with phosphorus or the like.
Type inversion layers 9a and 9b are formed as virtual electrodes,
Immediately below it is the buried channel described above. The operation principle of the light receiving section 1 is the same as that described in FIG.

Then, in order to control the surplus charges in the light receiving cells, the N ^-- type semiconductor layer 13 is provided with an N-type semiconductor layer 13 between adjacent cells.
^An AB drain 12 including a ⁺ type drain region 15 and a P ⁻ type potential barrier region 16 surrounding the drain region is formed in contact with the channel stopper region 3A on both sides. A polysilicon gate 18 is deposited on the drain region 15 of the AB drain 12 through a contact hole 17, and a voltage is applied from a metal electrode 21 through a via hole 20 of an insulating layer 19 to a predetermined potential barrier potential. Give rise to.

That is, a predetermined voltage is applied from the electrode 21 to the gate 18 to make the N ⁺ type drain region 15 have the same potential as the gate 18, and the P ⁻ type potential barrier region 16 is provided by this potential.
Of the channel regions 4a, 4b.
The excess charge 30 that exceeds the potential barrier formed in the vicinity 22 of the PN junction is absorbed by the N ⁺ type drain region 15 and is discharged through the gate 18 and the electrode 21.

However, in this lateral overflow drain type structure, a drain region for absorbing excess charges is used.
Since 15 has a function of absorbing charges, when the CCD is used as a light receiving element, the drain region 15 (further, the gate 18) does not function as a light receiving portion and becomes a dead region. Therefore, the aperture ratio of the light receiving portion is only about 85%, which is not yet sufficient.

Also, when used as an analog memory, the drain region 15 does not work as a charge storage region, and therefore the basic characteristics (dynamic range) of the CCD are insufficient despite the high necessity.

On the other hand, according to the vertical overflow drain type shown in FIG. 16, a P-type well 32 is formed in an N-type silicon substrate 31, and in this P-type well, an N ⁺ -type impurity diffusion region 33 and further a P-type well are formed. ⁺⁺ type impurity diffusion region 36 is formed,
Photodiode PD with PN junction (J) is a photosensitive area
38 (pixels), and the P ⁺ -type impurity diffusion region 37 and the N-type impurity diffusion region 34 form a vertical register 48 corresponding to the storage unit 2 shown in FIG. 11 in the cell. .

The carriers generated in the photosensitive area 38 are sent to the vertical register 48 via the reading channel 47 and stored therein. The cell having the photosensitive area 38 and the register 48 is P
It is separated from the adjacent cell by the ⁺ type channel stopper region 35. Then, on the front surface side, the Si ₃ N ₄ layer 40 and the SiO ₂ layer 41 are laminated as the gate insulating film 42 on the SiO ₂ layer 39, the transfer electrode 43 serving as the gate of the register is provided, and the interlayer insulating film 44 is formed. The light-shielding layer 45 is formed therethrough.
Further, the photosensitive region 38 is covered with the above-described interlayer insulating film 44.

Then, the potential barrier for absorbing the excess charge in the light receiving cell is formed in the region 38 immediately below the N ⁺ type region 33, which is controlled by the potential of the substrate 31 (substrate potential), and the excess charge is formed. 50 is absorbed in the direction of the substrate 31.

However, in the case of this vertical overflow drain type, the aperture ratio of the cell is only about 15 to 30% due to the existence of the above-mentioned light shielding layer 45, and a microlens (not shown) is used to improve this. No.), it is necessary to collect the incident light (however, since it is not necessary to provide the memory section (storage section 2 shown in FIG. 11), the CCD element size is reduced), and the substrate under the region 38 Since the region becomes a dead region, the infrared sensitivity is extremely reduced. Therefore, although it is suitable for color imaging, infrared light including near infrared cannot be used as incident light and is not suitable for use in an infrared sensor.

Further, since the thickness or depth of the barrier region 38 is restricted, the capacity determined in the depth direction is limited and becomes small. This narrows the dynamic range and makes it easier for charges to leak to adjacent cells, degrading imaging performance.

[0022]

SUMMARY OF THE INVENTION It is an object of the present invention to improve quantum efficiency such as effectively expanding a light receiving region and ensuring infrared sensitivity, and improve dynamic range by increasing capacitance, and It is an object of the present invention to provide a charge-coupled semiconductor device that can respond to the miniaturization of elements.

[0023]

That is, according to the present invention, a channel region (for example, N ^- type channel regions 64a and 64b described later:
The same applies to the following) and the potential barrier region 82 formed on the surface side of the channel region (for example, the P ⁻ -type impurity diffusion region 76 described later and the N ⁻ -type channel regions 64a and 64b described later: And a surplus charge absorption layer formed in contact with the surface of this potential barrier region and absorbing surplus charges in the charle region via the potential barrier region (for example, an N ⁺ -type polysilicon layer 75 described later: The same shall apply hereinafter)
The present invention relates to a charge coupled semiconductor device such as D.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION In the charge-coupled semiconductor device of the present invention, the first conductivity type first device as the channel region is used.
A channel region (for example, an N ⁻ type channel region 64a described later:
The same applies to the following) and the second channel region of the first conductivity type (for example, an N ⁻ type channel region 64b described later: the same applies hereinafter) is the second
They are separated from each other by a conductive type isolation region (for example, a P ⁺ type channel stopper region 63A to be described later: hereinafter the same), and potential barrier regions are formed in the first and second channel regions in contact with both sides of the isolation region. It is preferable that the surplus charge absorption layer is formed on the surfaces of the separation region and the potential barrier regions.

In addition, a plurality of charge transfer electrodes (for example, a polysilicon gate 5 to be described later; hereinafter the same) are intermittently arranged in the charge transfer direction of the channel region, and a potential distribution is present in the channel region between these charge transfer electrodes. Second for fixing
A conductive type semiconductor region (for example, a P ⁺ type inversion layer 69a described later,
69b or virtual electrode: the same applies hereinafter), and such a semiconductor region for fixing the potential distribution is formed between the potential barrier region and the second conductivity type channel stopper region. Is desirable.

Further, the first channel region of the first conductivity type and the second channel region of the first conductivity type are separated from each other by the channel stopper region of the second conductivity type, and a charge of the channel region is formed. A plurality of the charge transfer electrodes are arranged intermittently in the transfer direction, the second conductivity type semiconductor region for fixing the potential distribution is formed in the channel region between the charge transfer electrodes, and the surface of the semiconductor region is formed. The surplus charge absorption layer may be formed in contact with each other.

Then, the potential barrier region and the surplus charge absorption layer form a light receiving portion (for example, a light receiving cell 71 described later).
The light receiving section consisting of: the same hereinafter), and a charge storage section (for example, the storage section 2 shown in FIG. 11) adjacent to the light receiving section.
May be provided.

Alternatively, a semiconductor layer (for example, a P-type well 32, which will be described later, which will be described later) having a conductivity type opposite to that of the semiconductor substrate (for example, an N-type silicon substrate 31, which will be described later) is formed, and a PN junction is formed on this semiconductor layer. To form a photocarrier generation region (for example, a photosensitive region 38 described below: hereinafter), and a surplus charge absorption layer (for example, an N ⁺ -type polysilicon layer 95 described below: hereinafter, in contact with the surface of the photocarrier generation region). As well) may be formed.

In this case, a charge storage register area (for example, a vertical register 4 to be described later) is provided near the photocarrier generation area.
8) is formed, and the accumulated charge may be transferred by the charge transfer electrode.

In the charge-coupled semiconductor device of the present invention, specifically, the height of the potential barrier in the potential barrier region is controlled by the voltage applied to the surplus charge absorption layer, and surplus charges in the cell can be efficiently absorbed. To configure.

In this case, if the surplus charge absorbing layer is made of an incident light transmitting material, the incident light can efficiently enter the cell through the surplus charge absorbing layer.

[0032]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to Examples.

FIGS. 1 to 8 show a first embodiment in which the present invention is applied to a frame transfer type virtual phase CCD (however, in a portion common to the conventional example shown in FIGS. 11 to 15). Is attached with a common symbol, and the description thereof may be omitted).

The basic layout of the CCD according to the present embodiment is the same as that shown in FIG. 11, but as shown in FIGS. 1 to 3, each N ⁻ is separated by the channel stopper region 63 in the light receiving portion. A large number of polysilicon transfer gates 5 that are substantially orthogonal to the charge transfer directions of the mold channel regions 64a and 64b are intermittently arranged at a predetermined pitch, and inversion layers 69a and 69b as virtual electrodes are formed by impurity doping between the transfer gates. Has become.

These inversion layers 69a and 69b are formed as P ⁺ -type virtual electrodes by doping with boron or the like, and the buried channel is directly under the virtual electrodes. The operation principle of the light receiving section is the same as that described in FIG.

Then, in order to control the surplus charges in the light receiving cells, the P ⁺ type channel stopper region 63 is formed between the adjacent cells.
It is completely separated by A (that is, the channel stopper region 3A in FIG. 13 is extended), and P ⁻ -type potential barrier regions 76 are formed on both sides of the channel stopper region 63A. 76 and 63A
A drain layer 75 of N ⁺ type polysilicon is formed on the surface of the drain layer 75 via a contact hole 77 to form an AB drain 72 for absorbing excess charges. This AB
A voltage is applied to the drain layer 75 of the drain 72 from the electrode 81 via the via hole 80 of the insulating layer 19 to generate a predetermined potential barrier potential.

That is, when a predetermined voltage is applied from the electrode 81 to the drain layer 75, this potential causes a gap between the drain layer 75 and the potential barrier region 76-well 73 near the PN junction (potential barrier 82) and the well 73. , FIG. 4 (a)
A potential as shown in (3) is formed, and the excess charge 60 in the well 73 gets over the potential barrier 82 and is sucked into the drain layer 75. Then, the absorbed charges are discharged through the electrode 81.

Further, the adjacent cells 71-71 are completely insulated and separated by the potential barrier by the channel stopper region 63A, and the leakage of charges does not occur. Even if there is a charge that tries to cross the potential barrier, this is the channel stopper region.
It is absorbed from 63A to the drain layer 75 and does not enter the adjacent cell.

In the above cell structure, the size of each cell is 6 in the area of the virtual electrodes 69a and 69b.
˜7 μm × 6 to 7 μm, the width w ₁ of the channel stopper region 63A is about 0.8 μm, and the width w of the potential barrier region 76.
₂ may be about 0.5 μm, and the width w ₃ of the drain layer 75 may be about ₃ μm. Regarding the impurity concentration, the channel stopper region 63A is about 10 ¹⁷ pieces / cm ³ , the potential barrier region 76 is about 10 ¹⁶ pieces / cm ³ , and the drain layer 75 is 10 ²⁰ pieces / cm ^3.
Degree.

In order to manufacture the light receiving portion of the CCD of this embodiment, first, as shown in FIG. 5, the P ^-- type silicon substrate 14 is used.
An N ⁻ type well 73 is formed by a diffusion method, and then a P ⁺ type inversion layer 69 is formed using a mask (not shown) as shown in FIG.
The a, 69b and the P ⁻ type semiconductor region 76 are selectively formed.

Next, as shown in FIG. 7, deep impurity diffusion is performed using the SiO ₂ layer 90 as a mask to form P ⁺ type channel stopper regions 63 and 63A, and the channel stopper region 63 is formed.
The P ⁻ type semiconductor region 76 is divided into both sides by A, and each is used as a potential barrier region.

Next, as shown in FIG. 8, a gate oxide film 10 is formed on the surface, and an opening 77 is formed over the channel stopper region 63A and the potential barrier region 76.
Are selectively formed, and then CVD (Chemical Vapor Deposi
phosphorus-doped polysilicon is deposited by a photolithography method and etched by a photolithography technique to deposit an N ⁺ -type polysilicon barrier layer 75 in the opening (contact hole) 77.

Thereafter, as shown in FIG. 2, a SiO ₂ layer 19 is deposited on the entire surface by a CVD method, a via hole 80 is formed on the SiO ₂ layer 19 by a photolithography technique, and a metal electrode 81 is selectively deposited. To do.

Compared with the lateral overflow drain type structure shown in FIGS. 13 to 15, the CCD according to this embodiment has a drain layer 75 made of N ⁺ type polysilicon as an excess charge absorbing layer of the AB drain 72. On the surface of well 73,
That is, since the charges are formed on the surfaces of the channel stopper region 63A and the potential barrier region 76, the excess charges in the well 73 are discharged to the drain layer 75 above the potential barrier determined by the potential barrier region 76. Become.

The height of this potential barrier is controlled by the voltage applied to the polysilicon layer 75, which can effectively absorb and remove the excess charge, has no drain layer in the well 73, and is not Since the silicon layer 75 allows incident light to pass therethrough, the lower portion of the polysilicon layer 75 is also a normal CCD.
Function as a part of the light receiving part of the. Therefore, the above-mentioned dead region can be completely removed from the light receiving element,
The aperture ratio improves to almost 100%. When the aperture ratio is the same, the cell size can be reduced and the size can be reduced as compared with the conventional structure. The electrode 81 also transmits incident light, such as polysilicon or ITO (Indium tin oxid).
e) consists of.

In this way, the drain layer 75 is formed in the channel region.
Since it is installed away from 64a and 64b (well 73), CCD
The area efficiency when receiving light is significantly improved, but the specific effects are summarized below.

(1) By increasing the light receiving region, the quantum efficiency of photoelectric conversion of incident light can be improved and the infrared sensitivity can be secured.

(2) Since the aperture ratio is improved, the device can be downsized.

(3) Since charges can be generated by incident light not only in the well 73 but also in the P ^-- type region 76, the well capacity is increased and the dynamic range of the CCD is improved.

(4) In addition to the increase in well capacitance, the adjacent cells are completely separated by the channel stopper region 63A, and the drain layer 75 is formed in contact with the channel stopper region 63A. There is no charge leakage
The CCD performance can be kept good.

(5) The drain layer 75 is made of polysilicon. Since such a drain layer is used for CCD, it is not required to have quality such as crystallinity, so polysilicon is used. However, there is no problem, and it is preferable in consideration of its optical transparency and film forming property.

(6) Further, as understood from the above-mentioned manufacturing process, since the manufacturing process is very similar to the current process, there is no need for major changes in the process or special materials, and the process is simple and low. Can be implemented at cost.

FIG. 9 shows a second embodiment in which the present invention is applied to a frame transfer type virtual phase CCD.

According to this embodiment, as compared with the structure shown in FIG. 1, the N ⁺ -type polysilicon drain layers 75a and 75b each function as a potential barrier region.
^{The difference is that the +} type inversion layers 69a and 69b are in contact with the surfaces and are formed directly thereon. However, in the portions corresponding to FIG. 1, a and b are attached to common numerals depending on the inversion layers 69a and 69b.

As described above, even if the drain layers 75a and 75b are provided in each cell independently, the excess charge 60 in each cell is
Since the a and 60b are absorbed and removed by the drain layers 75a and 75b, exceeding the potential barrier between the inversion layers 69a and 69b and the well 73 due to the voltage applied to the drain layers 75a and 75b, respectively, the first embodiment described above is performed. The same effect as the example can be obtained. Since the P ⁻ type region 76 is not provided, the cell size can be further reduced.

FIG. 10 shows a third embodiment in which the present invention is applied to a CCD having a cell structure similar to that of the conventional example of FIG.

In this embodiment, parts common to those of the conventional example of FIG. 16 are designated by common reference numerals and their explanations are omitted. However, as a configuration which is significantly different, the potential in the N ⁺ type region 33 on the light receiving side is set. In contact with the surface of the P ⁺⁺ type region 36 as the barrier region, the N ⁺ is formed through the contact hole 97 of the interlayer insulating film 44.
Type polysilicon layer 95 is deposited as a drain layer for excess charge, and via hole 101 of interlayer insulating film 100 is further formed thereon.
That is, the incident light-transmissive electrode 91 is adhered via.

Therefore, the surplus charge 50 generated in the well 32 is
A is absorbed by the drain layer 95, absorbed, and removed. As a result, it is possible to eliminate the insensitive region that lowers the infrared sensitivity as described with reference to FIG. 16, so that the infrared sensitivity can also be improved. Moreover, since the excess charge can be effectively absorbed, the thickness of the well 32 is increased,
The capacitance in the depth direction of the substrate can be increased, and the leakage of charges to adjacent cells can be reduced.

Although the present invention has been described with reference to the embodiments, various modifications can be made to the above embodiments based on the technical idea of the present invention.

For example, the above-mentioned channel stopper region,
The cross-sectional shape and the planar pattern shape, position, and size of the potential barrier region, the drain layer, etc. may be variously changed. Polysilicon is suitable as the material of the drain layer, but other light transmissive materials may be used. You may form.

As the AB drain described above, a horizontal overflow drain type and a surface recombination type (E
HR) and the like can also be used. Further, it is possible to convert the conductivity type of each semiconductor region forming the above-mentioned CCD to the opposite conductivity type.

The present invention can also be applied to optical devices such as photoelectric conversion elements such as the above-mentioned CCD.

[0063]

As described above, the present invention is in contact with the surface of the potential barrier region formed on the surface side of the channel region and absorbs the excess charge in the channel region through the potential barrier region. Since the surplus charge absorption layer is provided, the surplus charge absorption layer is provided apart from the channel region, and the area efficiency of the device when receiving light is significantly improved, and the following specific effects are achieved. Will be things.

(1) By increasing the light receiving region, the quantum efficiency of photoelectric conversion of incident light can be improved and the infrared sensitivity can be secured.

(2) Since the aperture ratio is improved, the element can be downsized.

(3) Since the charge generation region due to incident light is increased, the capacity is increased and the dynamic range of the device is improved.

[Brief description of drawings]

FIG. 1 is a sectional view (a sectional view taken along line I-I of FIG. 2) of a main part of a light receiving portion of a CCD according to a first embodiment of the present invention and an enlarged view of a part thereof.

FIG. 2 is a plan view of a main part of the light receiving unit.

FIG. 3 is a sectional view taken along line III-III in FIG.

4 (a) is a potential distribution curve diagram along (A ')-(A ")-(A) in FIG. 2, and (b) is (B')-in FIG.
It is a potential distribution curve figure which follows (B ")-(B).

FIG. 5 is a cross-sectional view of a main part showing a step in the manufacturing process of the light-receiving unit.

FIG. 6 is a cross-sectional view of a main part showing another stage of the manufacturing process.

FIG. 7 is a cross-sectional view of a main part showing another stage of the manufacturing process.

FIG. 8 is a cross-sectional view of a main part showing still another stage of the manufacturing process.

FIG. 9 is a sectional view of an essential part of a light receiving portion of a CCD according to a second embodiment of the present invention.

FIG. 10 is a sectional view of an essential part of a CCD according to a third embodiment of the present invention.

11A and 11B are a schematic plan view and a photoelectric conversion characteristic diagram of a CCD according to a conventional example and a main part thereof.

FIG. 12 is an operation principle diagram of a light receiving unit in the CCD.

FIG. 13 is a plan view of a main part of a light receiving section of the CCD.

14 is a sectional view taken along line XIV-XIV in FIG. 13.

15 is a sectional view taken along line XV-XV in FIG. 13.

FIG. 16 is a cross-sectional view of a main part of a CCD according to another conventional example.

[Explanation of symbols]

5 ... Transfer gate 14 ... Silicon substrate 60 ... Excess charge 63, 63A ... Channel stopper regions 64a, 64b ... Channel regions 69a, 69b ... Inversion layer (virtual electrode) 71 ...・ Light receiving cell 72 ・ ・ ・ AB drain 73 ・ ・ ・ Well 75 ・ ・ ・ Drain layer 76 ・ ・ ・ Potential barrier region 78 ・ ・ ・ Drain layer (N ⁺ type polysilicon layer) 81 ・ ・ ・ Electrode 82 ・ ・ ・Potential barrier

Claims (10)

[Claims] 1. A channel region, a potential barrier region formed on the surface side of the channel region, and a surplus charge in the channel region which is formed in contact with the surface of the potential barrier region and is formed on the potential barrier region. A charge-coupled semiconductor device having a surplus charge absorption layer that absorbs via a charge-coupled semiconductor device. 2. A first conductivity type first channel region and a first conductivity type second channel region are separated from each other by a second conductivity type isolation region, and each potential barrier is in contact with both sides of the isolation region. The semiconductor device according to claim 1, wherein regions are formed in the first and second channel regions, and a surplus charge absorption layer is formed in contact with the surfaces of the isolation region and each of the potential barrier regions. 3. A plurality of charge transfer electrodes are intermittently arranged in the charge transfer direction of the channel region, and a second conductivity type semiconductor region for fixing a potential distribution is formed in the channel region between these charge transfer electrodes. The semiconductor device according to claim 2, wherein 4. The semiconductor device according to claim 3, wherein the potential distribution fixing semiconductor region is formed between the potential barrier region and the second conductivity type channel stopper region. 5. A first conductivity type first channel region and a first conductivity type second channel region are separated from each other by a second conductivity type channel stopper region, and a plurality of charge transfers are performed in a charge transfer direction of the channel region. Electrodes are arranged intermittently, a second conductivity type semiconductor region for fixing potential distribution is formed in a channel region between these charge transfer electrodes, and a surplus charge absorption layer is formed in contact with the surface of this semiconductor region. The semiconductor device according to claim 1, wherein 6. The potential barrier region and the surplus charge absorption layer are formed in the light receiving portion, and the charge accumulating portion is arranged adjacent to the light receiving portion. Semiconductor device. 7. A semiconductor layer having a conductivity type opposite to that of the semiconductor substrate is formed on the semiconductor substrate, a photocarrier generation region is formed by a PN junction in the semiconductor layer, and a surplus charge is absorbed in contact with the surface of the photocarrier generation region. A layer is formed, Claim 1
The semiconductor device described in. 8. The semiconductor device according to claim 7, wherein a charge storage register region is formed near the photocarrier generation region, and the stored charge is transferred by the charge transfer electrode. 9. The semiconductor device according to claim 1, wherein the height of the potential barrier in the potential barrier region is controlled by the voltage applied to the surplus charge absorption layer. 10. The semiconductor device according to claim 9, wherein the excess charge absorption layer is made of an incident light transmissive material.