WO1991015875A1 - Two phase ccd for interline image sensor - Google Patents

Two phase ccd for interline image sensor Download PDF

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Publication number
WO1991015875A1
WO1991015875A1 PCT/US1991/002058 US9102058W WO9115875A1 WO 1991015875 A1 WO1991015875 A1 WO 1991015875A1 US 9102058 W US9102058 W US 9102058W WO 9115875 A1 WO9115875 A1 WO 9115875A1
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WO
WIPO (PCT)
Prior art keywords
electrodes
image sensor
ccd
sensor device
buried channel
Prior art date
Application number
PCT/US1991/002058
Other languages
French (fr)
Inventor
David Losee
Original Assignee
Eastman Kodak Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Company filed Critical Eastman Kodak Company
Publication of WO1991015875A1 publication Critical patent/WO1991015875A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14831—Area CCD imagers

Definitions

  • This invention relates to image sensing devices and, more particularly, to interline transfer type charge coupled imagers which use two phase buried channel CCDs .
  • This vertical shift register is composed of buried channel 40, electrodes 20 and 30 which are connected to vertical clock ⁇ , , and electrodes 50 and 60 which are connected to vertical clock ⁇ 2 • These electrodes are separated from the substrate semiconductor 70 by an insulating layer 80.
  • the regions 65 beneath electrodes 30 and 60 are ion implanted to provide a potential energy difference between regions 25 and 26, controlled by the ⁇ ., clock, and between regions 55 and 56, controlled by the ⁇ 2 clock.
  • the imaging device is operated in an interlaced mode where a first field of photocharge from sites on, say, odd numbered rows of photosites, is read out and, subsequently, sites on even numbered rows are read out as a second field. For example, all photosites addressed by the ⁇ , clock are read out, and then as the second field, those addressed by the ⁇ 2 clocks, are read out.
  • the design requires two electrodes for each row of imaging sites. For example, see U.S. Patent No. 4,908,518 which describes a particular two phase CCD with overlapping electrodes.
  • Such a structure is subject to yield limitations due to short circuits, caused by photomasking imperfections, incomplete etching of the electrode materials, etc. between electrodes of either the first or second levels of polysilicon.
  • the object of this invention to provide an image sensor with simplified pixel design.
  • This object is achieved in an image sensor device having an array of columns and rows of separate pixels and wherein charge collected in a pixel is transferred into a two phase buried channel CCD, such CCD comprising lightly droped uniform buried channel, a series of overlapping electrodes, with each electrode formed from a single level of conductor, separate voltage clocks ⁇ -, and ⁇ 2 being connected to alternate electrodes, doped spaced storage, regions in the buried channel being formed under the electrodes, and means for transferring charge from each pixel into such region under its corresponding electrode, characterized in that the buried channel is provided with no further doped potential barrier region under the electrodes.
  • the potential energy distribution which is necessary to provide directionality for charge transfer in the CCD channel, is formed by, first, implantation of do
  • FIG. 1 is a plan view of a typical prior art imaging device
  • FIG. 2 is a fragmentary, partially schematic vertical section view through a semiconductor device, taken along the lines A-A of FIG. 1, illustrating a prior art construction
  • FIGS. 3a through 3c are plan views illustrating the present invention
  • FIGS. 4a, 4b and 4c are a fragmentary, partially schematic cross-sectional views taken along the lines A-A' , B-B and C-C of FIG. 3c respectively;
  • FIG. 4d is a schematic potential energy diagram for the FIG. 4 embodiment;
  • FIG. 5 is a schematic of the timing of the vertical clock voltages required for operation of a p-channel embodiment of the present invention.
  • FIG. 3 and 4 A first embodiment of the invention as a p-channel CCD device is illustrated schematically by FIG. 3 and 4.
  • an n-type semiconductor substrate 100 is provided with channel stop regions 110 and lightly doped uniform buried channel regions 120 as shown in plan view in FIG. 3a and in cross-sectional views in FIG. 4.
  • An insulating oxide 125 is grown over the semiconductor surface and a first layer of polysilicon conductor 130 is deposited.
  • a storage region is provided by implantation of boron ' into regions 140 by methods such as described by Losee et al in U.S. Patent No. 4,613,402, and illustrated in FIG. 3b.
  • FIGS. 4a, 4b and 4c are cross—sectional views taken along the lines A'-A* , B-B and C-C respectively of FIG. 3c. It is to be appreciated that this construction thus consists of a single conducting electrode being associated with each row of pixels, thus providing a simplified pixel design.
  • a further advantage of the two-phase CCD construction is the reduction in the number of contacts which need to be provided for connection of the gate electrodes to the clocking voltages and, as discussed by Losee et al, U.S. Patent 4,613,402, a reduced sensitivity to electrical intralevel gate electrode leakages.
  • FIG. 4d shows schematically the potential energy distribution along the CCD channel cross—section of FIG. 4b where the charge carriers are holes and the clock voltage ⁇ , is more positive than clock voltage ⁇ 2 ⁇ Also indicated schematically in FIG. 4d is the transfer of photogenerated holes from the storage regions 140 under the ⁇ ,, electrodes to the storage regions 160 under the ⁇ 2 electrodes. It will be appreciated that it is important to insure that no extraneous potential wells or barriers exist in the transition regions, such as region 162, at and near the boundaries between the ⁇ -, and ⁇ 2 electrodes.
  • Operation of the device is as follows: Light incident on the photosites 180 and 190 is absorbed and generates electron hole pairs. The photogenerated holes are collected by the electric fields surrounding sites 180 and 190. Designating the array of pixels 180 as the odd field and the array of pixels 190 as the even field, a vertical clocking sequence such as indicated in FIG. 5 may be used to read out the image information. At the end of a period of time, a negative voltage is applied to one of the electrodes, for example electrode 130, and photocharges from regions 180 are transferred to the storage regions under electrode 130, regions 121 of FIG. 4b in this case. Electrodes 130 and 170 are then clocked to sequentially transfer these photocharges to charge detection circuitry as is well known to those skilled in the art.
  • the second field of photosites, 190 is read out by applying a negative voltage to electrode 170, thus transferring photocharges to the storage regions 122, under electrode 170.
  • electrodes 130 and 170 are clocked to sequentially transfer photocharges from all such photosites 190 to charge detection circuitry.
  • the complete frame of photogenerated charges is thus read out as a pair of, so called, interlaced fields.
  • a second embodiment of this invention is an n-channel device wherein the semiconductor substrate region 100 is p—type, the buried channel 120 is 'provided by adding donor type impurities, storage regions 140 and 160 are produced by ion implantation and diffusion of Arsenic atoms such as described by Rhodes, U.S. Patent No. 4,742,016, and photocharge - collection sites 180 and 190 are provided by implantation of donor type impurities. It is understood that operation of such an n-channel device would require appropriate changes in polarity of the clocking voltages as is well known to those skilled in the art.
  • the second embodiment of the invention offers the advantage that the lightly doped channel 120 may be formed by implantation of arsenic atoms and that the doping of the storage regions is also provided with the same dopant specie, i.e., arsenic. It is well known that arsenic is a slowly diffusing impurity even at elevated temperatures, e.g., greater than 900°C. Thus the placement and diffusion of the dopant atoms for the transfer and storage regions of the CCD are more precisely controlled than for other dopant species. This feature facilitates construction of smaller pixels and thus contributes to a higher yield of satisfactorily performing devices or devices with higher resolution (i.e., more pixels per unit area) .
  • a third embodiment of the present invention is one where the conductive electrodes 130 and 170 of the figures are composed of composite layers of polysilicon covered with a metal silicide of the group consisting of WSi , MoSi , TaSi , TiSi X, W, Mo, or Ta.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

In interline transfer type image sensor devices, photogenerated charge is transferred from a collection node into a two phase buried channel charge coupled shift register. The CCD structure is composed of two overlapping levels of polysilicon, a lightly doped uniform buried channel and electrodes associated with each row of pixels. Doped spaced storage regions are formed under each electrode without further using doped potential barrier regions under the electrodes.

Description

-ι-
T Q- PHASE CCD FOR INTERLINE IMAGE SENSOR Cross-Reference to Related Application
Reference is made to commonly assigned U.S. Patent Application Serial No. 309,646 filed February 10, 1989 and entitled "Interline Transfer CCD Image Sensing Device with Electrode Structure for Each Pixel". Technical Field
This invention relates to image sensing devices and, more particularly, to interline transfer type charge coupled imagers which use two phase buried channel CCDs . Background Art
In interline transfer type imaging devices, photogenerated charge is collected on a pn junction or under the gate of a photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit. In an area array of such photocharge collection sites, or pixels, it is necessary to transfer the collected photocharge, first to a vertical shift register and then to a horizontal shift register, finally reaching a charge sensitive detector or amplifier. In prior art, such as, for example, U.S. 4,772,565, as indicated schematically in FIGS. 1 and 2, a given row of pixels 10 is addressed by application of a voltage to electrodes 20 and 30 which are both connected to the same vertical clock, Φ^. Upon application of this voltage, photocharge is transferred to the buried channel 40 of the vertical shift register. This vertical shift register is composed of buried channel 40, electrodes 20 and 30 which are connected to vertical clock φ, , and electrodes 50 and 60 which are connected to vertical clock Φ2• These electrodes are separated from the substrate semiconductor 70 by an insulating layer 80. The regions 65 beneath electrodes 30 and 60 are ion implanted to provide a potential energy difference between regions 25 and 26, controlled by the φ., clock, and between regions 55 and 56, controlled by the Φ2 clock. The imaging device is operated in an interlaced mode where a first field of photocharge from sites on, say, odd numbered rows of photosites, is read out and, subsequently, sites on even numbered rows are read out as a second field. For example, all photosites addressed by the φ, clock are read out, and then as the second field, those addressed by the Φ2 clocks, are read out. Overall, the design requires two electrodes for each row of imaging sites. For example, see U.S. Patent No. 4,908,518 which describes a particular two phase CCD with overlapping electrodes. Such a structure is subject to yield limitations due to short circuits, caused by photomasking imperfections, incomplete etching of the electrode materials, etc. between electrodes of either the first or second levels of polysilicon. Such short circuits can cause inoperability of the device. In order to avoid such short circuits, design tolerances are specified which limit the minimum pixel dimensions. Disclosure of the Invention It is the object of this invention to provide an image sensor with simplified pixel design. This object.is achieved in an image sensor device having an array of columns and rows of separate pixels and wherein charge collected in a pixel is transferred into a two phase buried channel CCD, such CCD comprising lightly droped uniform buried channel, a series of overlapping electrodes, with each electrode formed from a single level of conductor, separate voltage clocks Φ-, and Φ2 being connected to alternate electrodes, doped spaced storage, regions in the buried channel being formed under the electrodes, and means for transferring charge from each pixel into such region under its corresponding electrode, characterized in that the buried channel is provided with no further doped potential barrier region under the electrodes.- In this invention, the potential energy distribution, which is necessary to provide directionality for charge transfer in the CCD channel, is formed by, first, implantation of dopants into the semiconductor substrate to produce a lightly doped uniform buried channel and by, second, separate formation of storage regions in the CCD channel by ion implantations and/or diffusion. Brief Description of the Drawings
FIG. 1 is a plan view of a typical prior art imaging device;
FIG. 2 is a fragmentary, partially schematic vertical section view through a semiconductor device, taken along the lines A-A of FIG. 1, illustrating a prior art construction; FIGS. 3a through 3c are plan views illustrating the present invention;
FIGS. 4a, 4b and 4c are a fragmentary, partially schematic cross-sectional views taken along the lines A-A' , B-B and C-C of FIG. 3c respectively; FIG. 4d is a schematic potential energy diagram for the FIG. 4 embodiment; and
FIG. 5 is a schematic of the timing of the vertical clock voltages required for operation of a p-channel embodiment of the present invention. Modes of Carrying Out the Invention
A first embodiment of the invention as a p-channel CCD device is illustrated schematically by FIG. 3 and 4. Referring now to FIGS. 3 and 4, an n-type semiconductor substrate 100 is provided with channel stop regions 110 and lightly doped uniform buried channel regions 120 as shown in plan view in FIG. 3a and in cross-sectional views in FIG. 4. An insulating oxide 125 is grown over the semiconductor surface and a first layer of polysilicon conductor 130 is deposited. A storage region is provided by implantation of boron' into regions 140 by methods such as described by Losee et al in U.S. Patent No. 4,613,402, and illustrated in FIG. 3b. Turning now to FIG. 3c, an insulating layer of oxide is grown over the polysilicon conductor 130 and a second storage region 160 is provided by ion implantation of boron. A second layer of polysilicon conductor is deposited and patterned to form electrodes 170. Regions 180 and 190, which are not covered with the polysilicon electrodes are then implanted with appropriate impurities to form storage regions for collection of photogenerated charge. FIGS. 4a, 4b and 4c are cross—sectional views taken along the lines A'-A* , B-B and C-C respectively of FIG. 3c. It is to be appreciated that this construction thus consists of a single conducting electrode being associated with each row of pixels, thus providing a simplified pixel design.
A further advantage of the two-phase CCD construction is the reduction in the number of contacts which need to be provided for connection of the gate electrodes to the clocking voltages and, as discussed by Losee et al, U.S. Patent 4,613,402, a reduced sensitivity to electrical intralevel gate electrode leakages.
"FIG. 4d shows schematically the potential energy distribution along the CCD channel cross—section of FIG. 4b where the charge carriers are holes and the clock voltage φ, is more positive than clock voltage Φ2< Also indicated schematically in FIG. 4d is the transfer of photogenerated holes from the storage regions 140 under the φ,, electrodes to the storage regions 160 under the Φ2 electrodes. It will be appreciated that it is important to insure that no extraneous potential wells or barriers exist in the transition regions, such as region 162, at and near the boundaries between the Φ-, and Φ2 electrodes.
This is facilitated in the present embodiment by the implanted storage regions and the buried channel transfer regions 141 and 161 which are formed by the lightly doped buried channel 120. Because of the relatively long penetration distance for implanted boron atoms and the existence of the convenient precision alignment techniques described by Losee et al, U.S. Patent 4,613,402, it is more convenient to implant storage regions in this p—channel device. That is to say, in order to implant barrier regions in a p-channel device would require implantation of either phosphorous or arsenic atoms into the barrier regions. This could inconveniently require high implant energies because the implantation ranges for these atoms are considerably shorter than for boron.
Operation of the device is as follows: Light incident on the photosites 180 and 190 is absorbed and generates electron hole pairs. The photogenerated holes are collected by the electric fields surrounding sites 180 and 190. Designating the array of pixels 180 as the odd field and the array of pixels 190 as the even field, a vertical clocking sequence such as indicated in FIG. 5 may be used to read out the image information. At the end of a period of time, a negative voltage is applied to one of the electrodes, for example electrode 130, and photocharges from regions 180 are transferred to the storage regions under electrode 130, regions 121 of FIG. 4b in this case. Electrodes 130 and 170 are then clocked to sequentially transfer these photocharges to charge detection circuitry as is well known to those skilled in the art. Subsequently, the second field of photosites, 190, is read out by applying a negative voltage to electrode 170, thus transferring photocharges to the storage regions 122, under electrode 170. Again, electrodes 130 and 170 are clocked to sequentially transfer photocharges from all such photosites 190 to charge detection circuitry. The complete frame of photogenerated charges is thus read out as a pair of, so called, interlaced fields.
A second embodiment of this invention is an n-channel device wherein the semiconductor substrate region 100 is p—type, the buried channel 120 is 'provided by adding donor type impurities, storage regions 140 and 160 are produced by ion implantation and diffusion of Arsenic atoms such as described by Rhodes, U.S. Patent No. 4,742,016, and photocharge - collection sites 180 and 190 are provided by implantation of donor type impurities. It is understood that operation of such an n-channel device would require appropriate changes in polarity of the clocking voltages as is well known to those skilled in the art.
The second embodiment of the invention offers the advantage that the lightly doped channel 120 may be formed by implantation of arsenic atoms and that the doping of the storage regions is also provided with the same dopant specie, i.e., arsenic. It is well known that arsenic is a slowly diffusing impurity even at elevated temperatures, e.g., greater than 900°C. Thus the placement and diffusion of the dopant atoms for the transfer and storage regions of the CCD are more precisely controlled than for other dopant species. This feature facilitates construction of smaller pixels and thus contributes to a higher yield of satisfactorily performing devices or devices with higher resolution (i.e., more pixels per unit area) . -1- A third embodiment of the present invention is one where the conductive electrodes 130 and 170 of the figures are composed of composite layers of polysilicon covered with a metal silicide of the group consisting of WSi , MoSi , TaSi , TiSi X, W, Mo, or Ta.

Claims

CLAIMS :
1. An image sensor device having an array of columns and rows of separate pixels and wherein charge collected in a pixel is transferred into a two phase buried channel CCD, such CCD comprising a lightly doped uniform buried channel, a series of overlapping electrodes over such channel, with each electrode formed from a single level of conductor, separate voltage clocks φ, and Φ2 being - connected to alternate electrodes, doped spaced storage regions in the buried channel being formed under the electrodes, and means for transferring charge from each pixel into such region under its corresponding electrode, characterized in that the buried channel is provided with no further doped potential barrier region under the electrodes.
2. An image sensor device as in claim 1 wherein the conductor of each, electrode is formed of doped polysilicon.
3. An image sensor device as in claim 1, wherein edge self—aligned storage regions are formed by diffusion of arsenic atoms from implanted regions beneath the CCD electrodes.
4. A p—channel CCD image sensor device as in claim 1 wherein storage regions are formed by implantation of boron atoms beneath the CCD electrodes .
5. An image sensor device as in claim 1 wherein one or both of said electrodes are comprised of composite layers of polysilicon and one or more of a material selected from the group consisting of WSi X, MoSiX, TaSi Ji., TiSiX., ,' Mo, or Ta.
6. An image sensor device as in claim 1 where each pixel includes a photodiode.
PCT/US1991/002058 1990-04-04 1991-03-28 Two phase ccd for interline image sensor WO1991015875A1 (en)

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US504,462 1990-04-04

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0193977A2 (en) * 1985-02-07 1986-09-10 Koninklijke Philips Electronics N.V. Charge-coupled image sensor arrangement
US4613402A (en) * 1985-07-01 1986-09-23 Eastman Kodak Company Method of making edge-aligned implants and electrodes therefor
US4742016A (en) * 1987-03-30 1988-05-03 Eastman Kodak Company Method of manufacture of a two-phase CCD
US4908518A (en) * 1989-02-10 1990-03-13 Eastman Kodak Company Interline transfer CCD image sensing device with electrode structure for each pixel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0193977A2 (en) * 1985-02-07 1986-09-10 Koninklijke Philips Electronics N.V. Charge-coupled image sensor arrangement
US4613402A (en) * 1985-07-01 1986-09-23 Eastman Kodak Company Method of making edge-aligned implants and electrodes therefor
US4742016A (en) * 1987-03-30 1988-05-03 Eastman Kodak Company Method of manufacture of a two-phase CCD
US4908518A (en) * 1989-02-10 1990-03-13 Eastman Kodak Company Interline transfer CCD image sensing device with electrode structure for each pixel

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