JPS6365308U - - Google Patents

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Publication number
JPS6365308U
JPS6365308U JP16076686U JP16076686U JPS6365308U JP S6365308 U JPS6365308 U JP S6365308U JP 16076686 U JP16076686 U JP 16076686U JP 16076686 U JP16076686 U JP 16076686U JP S6365308 U JPS6365308 U JP S6365308U
Authority
JP
Japan
Prior art keywords
gate
resistor
band
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16076686U
Other languages
English (en)
Other versions
JPH0526808Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986160766U priority Critical patent/JPH0526808Y2/ja
Publication of JPS6365308U publication Critical patent/JPS6365308U/ja
Application granted granted Critical
Publication of JPH0526808Y2 publication Critical patent/JPH0526808Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】
第１図は、本考案の混合増幅回路の一実施例の
回路図であり、第２図は、従来の混合増幅回路の
一例の回路図である。 １２，１９〜２１，４１：抵抗、１８：ＦＥＴ
、Ｇ１：第１ゲート、Ｇ２：第２ゲート、４６〜
５０：端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. ＶＨＦバンド受信時に周波数混合器として、Ｕ
    ＨＦバンド受信時に高周波増幅器として動作させ
    る電界効果トランジスタを用いた混合増幅回路に
    おいて、前記電界効果トランジスタの第１ゲート
    を第１の抵抗を介して接地するとともに第２の抵
    抗を介して第２ゲートに接続し、この第１ゲート
    に高周波信号を入力するとともに受信バンドに応
    じて異なる電圧を与え、前記第２ゲートに第３の
    抵抗を介して前記電圧より高いバイアス電圧を与
    えたことを特徴とする混合増幅回路。
JP1986160766U 1986-10-20 1986-10-20 Expired - Lifetime JPH0526808Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986160766U JPH0526808Y2 (ja) 1986-10-20 1986-10-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986160766U JPH0526808Y2 (ja) 1986-10-20 1986-10-20

Publications (2)

Publication Number Publication Date
JPS6365308U true JPS6365308U (ja) 1988-04-30
JPH0526808Y2 JPH0526808Y2 (ja) 1993-07-07

Family

ID=31086453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986160766U Expired - Lifetime JPH0526808Y2 (ja) 1986-10-20 1986-10-20

Country Status (1)

Country Link
JP (1) JPH0526808Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03262308A (ja) * 1990-03-13 1991-11-22 Toshiba Corp デュアルゲート電界効果トランジスタ増幅回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5711811U (ja) * 1980-06-20 1982-01-21
JPS5936609U (ja) * 1982-08-31 1984-03-07 株式会社東芝 混合回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936609B2 (ja) * 1976-02-03 1984-09-05 住友化学工業株式会社 不飽和アミドの製造方法
JPS53147366A (en) * 1977-05-25 1978-12-22 Shin Meiwa Ind Co Ltd Inversion device of body

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5711811U (ja) * 1980-06-20 1982-01-21
JPS5936609U (ja) * 1982-08-31 1984-03-07 株式会社東芝 混合回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03262308A (ja) * 1990-03-13 1991-11-22 Toshiba Corp デュアルゲート電界効果トランジスタ増幅回路

Also Published As

Publication number Publication date
JPH0526808Y2 (ja) 1993-07-07

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