JPS6364908B2 - - Google Patents
Info
- Publication number
- JPS6364908B2 JPS6364908B2 JP56135142A JP13514281A JPS6364908B2 JP S6364908 B2 JPS6364908 B2 JP S6364908B2 JP 56135142 A JP56135142 A JP 56135142A JP 13514281 A JP13514281 A JP 13514281A JP S6364908 B2 JPS6364908 B2 JP S6364908B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- thyristor
- buried
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/102—Cathode base regions of thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明は埋込ゲート型ゲートターンオフ
(GTO)サイリスタ構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to buried gate gate turn-off (GTO) thyristor structures.
埋込ゲート型GTOサイリスタは、第1図に示
す通常の表面ゲート型に対して、第2図に示すよ
うに、P2ベース層中にエピタキシヤル成長法を
利用して埋込形成されたP2 +高濃度不純物層を分
散的に設け、該P2 +層をゲート層とする。第1図
に示す表面ゲート型GTOサイリスタはオフ特性
改善のために、カソードKが短柵状の幅の狭い構
造にしてN2エミツタ層が分割されるのに対して、
埋込ゲート型GTOサイリスタはP2 +埋込ゲート層
上に全面にN2エミツタ層が形成される。これは、
埋込ゲート型GTOサイリスタは、主電流がゲー
トスリツトSを流れ、P2 +ゲート部がサイリスタ
動作しないことを利用したものである。このた
め、埋込ゲート型GTOサイリスタはゲート・カ
ソード間短絡発生が少なくなつてその製造を容易
にするなどの利点もある。 In contrast to the normal surface gate type shown in Fig. 1, the buried gate type GTO thyristor is a P thyristor that is formed embedded in a P2 base layer using an epitaxial growth method, as shown in Fig. 2. A 2+ high concentration impurity layer is provided in a distributed manner, and the P 2+ layer is used as a gate layer. In the surface gate type GTO thyristor shown in Fig. 1, the cathode K has a short fence-like narrow structure and the N2 emitter layer is divided in order to improve off-state characteristics.
In a buried gate type GTO thyristor, an N 2 emitter layer is formed over the entire surface of the P 2 + buried gate layer. this is,
The buried gate type GTO thyristor utilizes the fact that the main current flows through the gate slit S and the P 2 + gate part does not operate as a thyristor. Therefore, the buried gate type GTO thyristor has the advantage that short circuits between the gate and the cathode are less likely to occur, making it easier to manufacture.
しかし、埋込ゲート型GTOサイリスタは、P2 +
埋込ゲート相当分がサイリスタ動作しないことか
ら、第3図に示すようにオンゲート電流Igtのう
ちP2 +埋込ゲートからサイリスタ動作しない部分
のN2エミツタ層へ流れる電流分Igt′はターンオン
動作に寄与しないこと、即ちオンゲート電流Igt
が必要以上に大きくなり、主電流ILとの比になる
ターンオン利得を下げることになる。このを減少
させるために、P2 +埋込ゲート面積を減らすこと
はそのP2 +層削除部分はサイリスタとして動作す
るためにターンオフ失敗を起し易くする。 However, a buried gate GTO thyristor has a P 2 +
Since the part corresponding to the buried gate does not operate as a thyristor, the part of the on-gate current I gt that flows from the P 2 + buried gate to the N 2 emitter layer, which is the part where the thyristor does not operate, is turned on, as shown in Figure 3. Does not contribute to operation, that is, on-gate current I gt
becomes larger than necessary, lowering the turn-on gain as a ratio to the main current I L. To reduce this, reducing the P 2 + buried gate area makes the P 2 + layer removed part more prone to turn-off failure to operate as a thyristor.
本発明は、上記事情に鑑みてなされたもので、
P2 +埋込ゲート層の総抵抗をオフゲート電流を引
き出すに必要な範囲に抑えて等価的に余分のP2 +
層を削除するようカソードN2層を分割又はP2 +層
中央部を形成せずにそれに対向するアノードP1
層を削除した分割構造にすることにより、オンゲ
ート電流を低減した埋込ゲート型GTOサイリス
タを提供することを目的とする。 The present invention was made in view of the above circumstances, and
By keeping the total resistance of the P 2 + buried gate layer within the range necessary to draw the off-gate current, equivalently the extra P 2 +
Split the cathode N 2 layer to remove the layer P 2 + the anode opposite it without forming the central part P 1
The purpose of this invention is to provide a buried gate type GTO thyristor with reduced on-gate current by having a divided structure with layers removed.
第4図は本発明の一実施例を示す。同図が第3
図と異なる部分は、P2 +埋込ゲート層はその面積
をオフゲート電流を引き出すに必要な範囲にして
無効のオンゲート電流が流れる中央部(斜線部
分)にはP2 +層を形成せず、この中央部直下には
P1エミツタ層を形成せずにN1ベース層として残
してアノード電極Aによつてシヨートする構造に
ある。 FIG. 4 shows an embodiment of the present invention. The same figure is the third
The difference from the diagram is that the area of the P 2 + buried gate layer is set to the range necessary to draw out the off-gate current, and no P 2 + layer is formed in the central part (shaded area) where the invalid on-gate current flows. Directly below this central part
The structure is such that the P1 emitter layer is not formed, but is left as the N1 base layer and is shot by the anode electrode A.
この構造において、P2 +埋込ゲート層の抵抗は
P2ベース抵抗に比して遥かに小さいためP2 +層削
除によりオンゲート電流の電流密度が増加する。
これに加えて、オンゲート電流の無効分も減少す
るためオンゲート電流Igtを低減することができ
る。さらに、P2 +埋込ゲート層を埋込形成するに
は通常エピータキシヤル成長を利用するが、P2 +
層の面積減少はオートドーピング減少効果を有し
てこれによるIgt低減を一層効果的にする。なお、
P2 +埋込ゲート層の削除部分直下はP1エミツタ層
が形成されずにトランジスタとしてのみ動作し、
素子のターンオフに際しても誤つたサイリスタ動
作を起すことがない。 In this structure, the resistance of the P2 + buried gate layer is
Since it is much smaller than the P 2 base resistance, the current density of the on-gate current increases by removing the P 2 + layer.
In addition to this, since the reactive portion of the on-gate current is also reduced, the on-gate current I gt can be reduced. Furthermore, although epitaxial growth is usually used to form a P 2 + buried gate layer, P 2 +
The reduction in the area of the layer has the effect of reducing autodoping, making the resulting I gt reduction more effective. In addition,
Directly below the deleted part of the P2 + buried gate layer, the P1 emitter layer is not formed and it operates only as a transistor,
Erroneous thyristor operation does not occur even when the device is turned off.
本実施例においては、オンゲート電流Igtの減
少率を第3図のそれに対して約60%を低減でき
た。 In this example, the rate of decrease in the on-gate current I gt was reduced by about 60% compared to that in FIG.
第5図は本発明の他の実施例を示す。同図が第
3図と異なる部分は、P2 +層のうちオンゲート電
流無効分になる中央部に対向するN2エミツタ層
を形成せずにP2 -層として残し、カソードエミツ
タのシヨートとならないようにSi酸化膜などの絶
縁膜によりカソード電極KとP2 -ベース層を分離
した点にある。 FIG. 5 shows another embodiment of the invention. The difference between this figure and FIG. 3 is that the N 2 emitter layer facing the central part of the P 2 + layer, which is the ineffective portion of the on-gate current, is not formed and is left as a P 2 - layer, and the short part of the cathode emitter is The point is that the cathode electrode K and the P 2 -base layer are separated by an insulating film such as a Si oxide film to prevent this from occurring.
この構造により、オンゲート電流無効分は低減
し、ゲートスリツト周囲付近でのオンゲート電流
密度が増加し、換言すればオンゲート電流Igtを
少なくしてターンオンできる。また、N2エミツ
タの度合を逆バイアスして素子のターンオフを起
させる際に、N2エミツタシヨートによる漏れ電
流増大を防止する。 With this structure, the on-gate current reactive component is reduced and the on-gate current density near the gate slit is increased. In other words, turn-on can be achieved with a reduced on-gate current I gt . Furthermore, when turning off the device by reverse biasing the degree of the N 2 emitter, an increase in leakage current due to the N 2 emitter short is prevented.
本実施例においては、オンゲート電流Igtの減
少率を第3図のそれに対して約70%を低減でき
た。 In this example, the rate of decrease in on-gate current I gt was reduced by about 70% compared to that in FIG.
このように本発明においては、P2 +埋込ゲート
のうちサイリスタ動作に寄与しない部分からN2
エミツタ層へ流れる電流を低減する構造とするた
め、オンゲート電流の無効分を低減してターンオ
ン利得を上げることができる。 In this way, in the present invention, N 2
Since the structure reduces the current flowing to the emitter layer, it is possible to reduce the reactive component of the on-gate current and increase the turn-on gain.
第1図は従来の表面ゲート型GTOサイリスタ
構造図aと一部斜面図b、第2図は従来の埋込ゲ
ート型GTOサイリスタ構造図aと一部斜面図b、
第3図は従来の埋込ゲート型GTOサイリスタに
おけるオンゲート電流を説明するための図、第4
図は本発明の一実施例を示す構造図、第5図は本
発明の他の実施例を示す構造図である。
A……アノード電極、K……カソード電極、G
……ゲート電極、P2 +……埋込ゲート層。
Fig. 1 is a structural diagram a of a conventional surface gate type GTO thyristor and a partially sloped view b; Fig. 2 is a structural diagram a of a conventional buried gate type GTO thyristor and a partially sloped view b;
Figure 3 is a diagram for explaining the on-gate current in a conventional buried gate GTO thyristor.
The figure is a structural diagram showing one embodiment of the present invention, and FIG. 5 is a structural diagram showing another embodiment of the present invention. A... Anode electrode, K... Cathode electrode, G
...Gate electrode, P 2 + ...Buried gate layer.
Claims (1)
高濃度不純物層P2 +を分散配置して該層P2 +をゲ
ート層とした埋込ゲート型ゲートターンオフサイ
リスタにおいて、サイリスタ動作に寄与しない上
記ゲート層の中央部分からN2エミツタ層に流れ
る電流を低減するよう該N2エミツタ層はゲート
層の中央部分に対向する部分を形成せずにP2ベ
ース層を残して分割形成しかつ分割部のP2ベー
ス層とカソード電極間に絶縁膜を形成した構造を
特徴とする埋込ゲート型ゲートターンオフサイリ
スタ。 2 P1N1P2N2の4層構造にしてP2ベース層中に
高濃度不純物層P2 +を分散配置して該層P2 +をゲ
ート層とした埋込ゲート型ゲートターンオフサイ
リスタにおいて、上記ゲート層はサイリスタ動作
に寄与しない中央部分からN2エミツタ層に流れ
る電流を低減するよう該中央部分を形成せずに
P2ベース層を残しかつ該中央部分に対向するア
ノードP1層は形成せずにN1ベース層として残し
た分割構造を特徴とする埋込ゲート型ゲートター
ンオフサイリスタ。[Claims] A four-layer structure of 1 P 1 N 1 P 2 N 2 , with a highly concentrated impurity layer P 2 + dispersed in the P 2 base layer, and the layer P 2 + used as a gate layer. In the embedded gate type gate turn-off thyristor, the N 2 emitter layer does not form a portion facing the center portion of the gate layer so as to reduce the current flowing from the center portion of the gate layer that does not contribute to the thyristor operation to the N 2 emitter layer. A buried gate type gate turn-off thyristor characterized by a structure in which a P 2 base layer is left in the split portion and an insulating film is formed between the P 2 base layer in the split portion and a cathode electrode. 2 A buried gate type gate turn-off thyristor with a four-layer structure of P 1 N 1 P 2 N 2 , with a highly concentrated impurity layer P 2 + dispersed in the P 2 base layer, and using the layer P 2 + as the gate layer. In this case, the gate layer is formed without forming the central portion so as to reduce the current flowing from the central portion that does not contribute to the thyristor operation to the N2 emitter layer.
A buried gate type gate turn-off thyristor characterized by a divided structure in which a P2 base layer is left and an anode P1 layer facing the central portion is not formed and left as an N1 base layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13514281A JPS5835973A (en) | 1981-08-28 | 1981-08-28 | Buried gate type gate turn-off thyristor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13514281A JPS5835973A (en) | 1981-08-28 | 1981-08-28 | Buried gate type gate turn-off thyristor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5835973A JPS5835973A (en) | 1983-03-02 |
JPS6364908B2 true JPS6364908B2 (en) | 1988-12-14 |
Family
ID=15144781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13514281A Granted JPS5835973A (en) | 1981-08-28 | 1981-08-28 | Buried gate type gate turn-off thyristor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5835973A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010232564A (en) * | 2009-03-27 | 2010-10-14 | Shindengen Electric Mfg Co Ltd | Three-terminal thyristor |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60152063A (en) * | 1984-01-20 | 1985-08-10 | Toyo Electric Mfg Co Ltd | Electrostatic induction thyristor |
JPS60253269A (en) * | 1984-05-29 | 1985-12-13 | Meidensha Electric Mfg Co Ltd | Gate turn-off thyristor |
JP2801127B2 (en) * | 1993-07-28 | 1998-09-21 | 日本碍子株式会社 | Semiconductor device and manufacturing method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5117680A (en) * | 1974-08-05 | 1976-02-12 | Hitachi Ltd | Geeto taan ofu sairisuta |
JPS5428579A (en) * | 1977-08-05 | 1979-03-03 | Hitachi Ltd | Field effect switching element |
JPS54131886A (en) * | 1978-04-04 | 1979-10-13 | Meidensha Electric Mfg Co Ltd | High-speed switching thyristor |
-
1981
- 1981-08-28 JP JP13514281A patent/JPS5835973A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5117680A (en) * | 1974-08-05 | 1976-02-12 | Hitachi Ltd | Geeto taan ofu sairisuta |
JPS5428579A (en) * | 1977-08-05 | 1979-03-03 | Hitachi Ltd | Field effect switching element |
JPS54131886A (en) * | 1978-04-04 | 1979-10-13 | Meidensha Electric Mfg Co Ltd | High-speed switching thyristor |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010232564A (en) * | 2009-03-27 | 2010-10-14 | Shindengen Electric Mfg Co Ltd | Three-terminal thyristor |
Also Published As
Publication number | Publication date |
---|---|
JPS5835973A (en) | 1983-03-02 |
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