JPS6253951B2 - - Google Patents
Info
- Publication number
- JPS6253951B2 JPS6253951B2 JP56192218A JP19221881A JPS6253951B2 JP S6253951 B2 JPS6253951 B2 JP S6253951B2 JP 56192218 A JP56192218 A JP 56192218A JP 19221881 A JP19221881 A JP 19221881A JP S6253951 B2 JPS6253951 B2 JP S6253951B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- mos transistor
- mos
- transistor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 13
- 239000010410 layer Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Description
【発明の詳細な説明】
発明の技術分野
本発明はMOSトランジスタの上にMOSトラン
ジスタを積層した三次元構造のMOS型集積回路
の改良に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement in a MOS type integrated circuit having a three-dimensional structure in which MOS transistors are stacked on top of MOS transistors.
発明の技術的背景
近年、微細加工技術の進歩によるLSIの集積度
の限界の解決策として、三次元回路素子が注目さ
れている。こうした技術は、今までの平面構造を
立体化し、五層、十層と重ねることにより素子と
しての集積度を一挙に引上げようとするものであ
る。Technical Background of the Invention In recent years, three-dimensional circuit elements have attracted attention as a solution to the limits of LSI integration due to advances in microfabrication technology. These technologies attempt to raise the degree of integration of devices at once by converting conventional planar structures into three-dimensional structures and stacking five or ten layers.
ところで、従来、上述した三次元構造のMOS
型集積回路としては第１図及び第２図に示すもの
が知られている。即ち、図中の１はｐ型半導体基
板である。この基板１の表面には該基板１を電気
的に分離するためのフイールド絶縁膜２が設けら
れている。このフイールド絶縁膜２により分離さ
れた島状の基板１領域（素子形成領域）にはn+
型のソース、ドレイン領域３，４が互に電気的に
分離して設けられている。これらソース、ドレイ
ン領域３，４間の基板１上にはゲート絶縁膜５を
介してゲート電極６が設けられている。こうした
基板１、ソース、ドレイン領域３，４、ゲート絶
縁膜５及びゲート電極６等により第１のMOSト
ランジスタを構成している。また、前記ゲート電
極６等を含む半導体基板１上にはSiO2等からな
る層間絶縁膜７が被覆されている。そして前記第
１のMOSトランジスタ上には該層間絶縁膜７を
介してｐ型半導体層８が選択的に設けられてい
る。このｐ型半導体層８にはn+型のソース、ド
レイン領域９，１０が互い電気的に分離して設け
られている。このソース、ドレイン領域９，１０
間の半導体層部分（半導体基部）８′上にはゲー
ト絶縁膜１１を介してゲート電極１２が設けられ
ている。こうした半導体層８、ソース、ドレイン
領域９，１０、ゲート絶縁膜１１及びゲート電極
１２等により第２のMOSトランジスタが構成さ
れる。 By the way, conventionally, the above-mentioned three-dimensional structure MOS
As the type integrated circuit, those shown in FIGS. 1 and 2 are known. That is, 1 in the figure is a p-type semiconductor substrate. A field insulating film 2 for electrically isolating the substrate 1 is provided on the surface of the substrate 1. The island-shaped substrate 1 region (element formation region) separated by this field insulating film 2 has n +
Source and drain regions 3 and 4 of the mold are provided electrically isolated from each other. A gate electrode 6 is provided on the substrate 1 between these source and drain regions 3 and 4 with a gate insulating film 5 interposed therebetween. The substrate 1, source and drain regions 3, 4, gate insulating film 5, gate electrode 6, etc. constitute a first MOS transistor. Further, the semiconductor substrate 1 including the gate electrode 6 and the like is covered with an interlayer insulating film 7 made of SiO 2 or the like. A p-type semiconductor layer 8 is selectively provided on the first MOS transistor with the interlayer insulating film 7 interposed therebetween. This p-type semiconductor layer 8 is provided with n + -type source and drain regions 9 and 10 electrically separated from each other. These source and drain regions 9 and 10
A gate electrode 12 is provided on the intermediate semiconductor layer portion (semiconductor base) 8' with a gate insulating film 11 interposed therebetween. The semiconductor layer 8, source and drain regions 9, 10, gate insulating film 11, gate electrode 12, etc. constitute a second MOS transistor.
背景技術の問題点
上述した従来のMOS型集積回路において、第
１のMOSトランジスタ上に層間絶縁膜７を介し
て設けた第２のMOSトランジスタではSOS構造
のものと同様、そのチヤンネル下の半導体基部
８′の電位が浮遊状態になるため、次のような欠
点を生じる。即ち、第２のMOSトランジスタの
ＶD―ＩD特性を調べると、第３図に示すように２
つのねじれ（kink）A1，A2が現われる。第１の
ねじれA1はドレイン電圧ＶDが高くなり、ドレイ
ン接合近傍に比較的強い電界が生じると、空間電
荷層で衝突電離が起こり、チヤンネル領域下のフ
ローテイング状態の半導体基部８′に多数キヤリ
アが供給される結果、閾値電圧が低下することに
より生じる。更に、ドレイン電圧ＶDが高くなる
と、半導体基部８′とソース領域９の電位差がソ
ース接合のビルトイン電圧を越え、ソース領域９
をエミツタ、ドレイン領域１０をコレクタ、半導
体基部８′をベースとする寄生バイポーラトラン
ジスタがオン状態となり、その結果として第２の
ねじれA2が生じる。また、トランジスタが高速
スイツチング動作をしている場合には、チヤージ
ポンピング現象が支配的となり、チヤンネル電流
の一部が少数キヤリヤとしての半導体基部８′に
注入される結果、半導体基部８′が逆バイアスさ
れ、閾値電圧が深くなり、伝搬遅延時間が大きく
なる。Problems with the Background Art In the conventional MOS integrated circuit described above, in the second MOS transistor provided on the first MOS transistor via the interlayer insulating film 7, the semiconductor base under the channel is similar to the SOS structure. Since the potential of 8' becomes floating, the following drawbacks occur. That is, when examining the V D -I D characteristics of the second MOS transistor, as shown in FIG.
Two kinks A 1 and A 2 appear. The first twist A1 is caused by the fact that when the drain voltage V D increases and a relatively strong electric field is generated near the drain junction, impact ionization occurs in the space charge layer, causing a large amount of ionization to occur in the floating semiconductor base 8' under the channel region. This occurs because the threshold voltage decreases as a result of the carrier being supplied. Furthermore, when the drain voltage V D increases, the potential difference between the semiconductor base 8' and the source region 9 exceeds the built-in voltage of the source junction, and the source region 9
A parasitic bipolar transistor with emitter , drain region 10 as collector, and semiconductor base 8' as the base is turned on, resulting in a second twist A 2 . Furthermore, when the transistor is performing high-speed switching operation, the charge pumping phenomenon becomes dominant, and a portion of the channel current is injected into the semiconductor base 8' as a minority carrier, resulting in the semiconductor base 8' being reversed. Biased, the threshold voltage becomes deeper and the propagation delay time increases.
発明の目的
本発明は第１のMOSトランジスタ上の第２の
MOSトランジスタにおける半導体基部の電位の
浮遊を解消したMOS型集積回路を提供しようと
するものである。Purpose of the Invention The present invention provides a second MOS transistor on a first MOS transistor.
The present invention aims to provide a MOS type integrated circuit in which the floating potential of the semiconductor base of a MOS transistor is eliminated.
発明の概要
本発明は積層された第２のMOSトランジスタ
の半導体基部を第１のMOSトランジスタが設け
られる半導体基板に接続させることにより、第２
のMOSトランジスタにおける半導体基部の電位
を基板側に取出せるようにして該半導体基部がフ
ローテイング状態になるのを解消した三次元構造
のMOS型集積回路を得るものである。SUMMARY OF THE INVENTION The present invention connects the semiconductor base of a stacked second MOS transistor to a semiconductor substrate on which a first MOS transistor is provided.
To obtain a MOS type integrated circuit having a three-dimensional structure in which the potential of the semiconductor base of a MOS transistor can be taken out to the substrate side, thereby eliminating the floating state of the semiconductor base.
発明の実施例 本発明を第４図〜第６図を参照して説明する。Examples of the invention The present invention will be explained with reference to FIGS. 4 to 6.
第４図は本発明のMOS型集積回路を示す平面
図、第５図は第４図の―線に沿う断面図、第
６図は第４図の―線に沿う断面図である。図
中の２１はフイールド絶縁膜２２により電気的に
分離された島領域を有する例えばｐ型の半導体基
板である。この基板２１の島領域（素子形成領
域）にはn+型のソース、ドレイン領域２３，２
４が互に電気的に分離して設けられている。これ
らソース、ドレイン領域２３，２４間の基板２１
部分（チヤンネル領域）上には、ゲート絶縁膜２
５を介してゲート電極２６が設けられている。こ
うしたｐ型半導体基板２１、ソース、ドレイン領
域２３，２４、ゲート絶縁膜２５及びゲート電極
２６等により第１のｎチヤンネルMOSトランジ
スタ２７が構成されている。前記ゲート電極２６
等を含む半導体基板２１上には層間絶縁膜２８が
被覆されている。 4 is a plan view showing a MOS integrated circuit of the present invention, FIG. 5 is a cross-sectional view taken along the line --- in FIG. 4, and FIG. 6 is a cross-sectional view taken along the line --- in FIG. 4. 21 in the figure is, for example, a p-type semiconductor substrate having an island region electrically isolated by a field insulating film 22. As shown in FIG. The island region (element formation region) of this substrate 21 has n + type source and drain regions 23 and 2.
4 are provided electrically separated from each other. A substrate 21 between these source and drain regions 23 and 24
A gate insulating film 2 is formed on the portion (channel region).
A gate electrode 26 is provided through the gate electrode 5 . A first n-channel MOS transistor 27 is constituted by the p-type semiconductor substrate 21, the source and drain regions 23 and 24, the gate insulating film 25, the gate electrode 26, and the like. The gate electrode 26
An interlayer insulating film 28 is coated on the semiconductor substrate 21 including the semiconductor substrate 21 and the like.
また、前記第１のｎチヤンネルMOSトランジ
スタ２７上には、前記絶縁膜２８を介してｐ型半
導体層２９が選択的に設けられている。このｐ型
半導体層２９は前記フイールド絶縁膜２２上に後
記するゲート電極の配列方向に一部延出してい
る。前記ｐ型半導体層２９にはn+型のソース、
ドレイン領域３０，３１が互に電気的に分離して
設けられている。これらソース、ドレイン領域３
０，３１間の半導体層部分（半導体基部）２９′
上には、ゲート絶縁膜３２を介してゲート電極３
３が設けられている。こうした半導体層２９、ソ
ース、ドレイン領域３０，３１、ゲート絶縁膜３
２及びゲート電極３３等により第２のｎチヤンネ
ルMOSトランジスタ３４が構成されている。そ
して、かかる第２のｎチヤンネルMOSトランジ
スタ３４におけるフイールド絶縁膜２２に延出し
たチヤンネル領域下の前記層間絶縁膜２８とフイ
ールド絶縁膜２２に亘る一部には、第４図及び第
６図に示す如く開孔部３５が設けられている。前
記第２のｎチヤンネルMOSトランジスタ３４の
チヤンネル領域が形成される半導体基部２９′は
前記開孔部３５の存在するｐ型半導体部３６を介
して前記半導体基板２１と接続されている。 Further, a p-type semiconductor layer 29 is selectively provided on the first n-channel MOS transistor 27 with the insulating film 28 interposed therebetween. This p-type semiconductor layer 29 partially extends on the field insulating film 22 in the direction in which gate electrodes are arranged, which will be described later. The p-type semiconductor layer 29 includes an n + type source,
Drain regions 30 and 31 are provided electrically isolated from each other. These source and drain regions 3
Semiconductor layer portion (semiconductor base) 29' between 0 and 31
A gate electrode 3 is formed on the top via a gate insulating film 32.
3 is provided. Such semiconductor layer 29, source and drain regions 30, 31, gate insulating film 3
A second n-channel MOS transistor 34 is composed of the gate electrode 2, the gate electrode 33, and the like. In the second n-channel MOS transistor 34 , a portion extending between the interlayer insulating film 28 and the field insulating film 22 under the channel region extending to the field insulating film 22 is covered with the structure shown in FIG. As shown in FIG. 6, an opening 35 is provided. A semiconductor base portion 29' in which a channel region of the second n-channel MOS transistor 34 is formed is connected to the semiconductor substrate 21 via a p-type semiconductor portion 36 in which the opening portion 35 is present.
このような構成によれば、第２のｎチヤンネル
MOSトランジスタ３４の半導体基部２９′は層間
絶縁膜２８とフイールド絶縁膜２２に設けた開孔
部３５内の半導体部３６を介してｐ型半導体基板
２１に接続されているため、半導体基板２１によ
り該ｎチヤンネルMOSトランジスタ３４の半導
体基部２９′の電極を取出すことができ、該半導
体基部２９′がフローテイング状態となるのを解
消できる。その結果、従来の三次元構造のMOS
型集積回路にみられるＶD―ＩD特性のねじれを防
止し、かつ高速動作時の伝播遅延の増大を防止し
た良好な特性を有するMOS型集積回路を得るこ
とができる。 According to such a configuration, the second n-channel
The semiconductor base 29' of the MOS transistor 34 is connected to the p-type semiconductor substrate 21 via the interlayer insulating film 28 and the semiconductor portion 36 in the opening 35 provided in the field insulating film 22. The electrode of the semiconductor base 29' of the n-channel MOS transistor 34 can be taken out, and the floating state of the semiconductor base 29' can be eliminated. As a result, the conventional three-dimensional structure of MOS
It is possible to obtain a MOS type integrated circuit having good characteristics that prevents distortion of the V D -I D characteristics seen in type integrated circuits and prevents increase in propagation delay during high-speed operation.
なお、上記実施例では第１、第２のMOSトラ
ンジスタとしてｎチヤンネルのものを用いたがｐ
チヤンネルの第１、第２のMOSトランジスタを
用いてMOS型集積回路を構成してもよい。 In the above embodiment, n-channel MOS transistors were used as the first and second MOS transistors, but p
A MOS type integrated circuit may be constructed using the first and second MOS transistors of the channel.
発明の効果
以上詳述した如く、本発明によれば高密度で優
れた素子特性を有する三次元構造のMOS型集積
回路を提供できるものである。Effects of the Invention As detailed above, according to the present invention, it is possible to provide a three-dimensionally structured MOS integrated circuit having high density and excellent device characteristics.
第１図は従来の三次元構造のMOS型集積回路
を示す平面図、第２図は第１図の―線に沿う
断面図、第３図は従来のMOS型集積回路におけ
る第１のMOSトランジスタ上に層間絶縁膜を介
して設けられた第２のMOSトランジスタのＶD―
ＩD特性を示す線図、第４図は本発明の一実施例
を示す三次元構造のMOS型集積回路の平面図、
第５図は第４図の―線に沿う断面図、第６図
は第４図の―線に沿う断面図である。
２１…ｐ型半導体基板、２２…フイールド絶縁
膜、２３，３０…n+型のソース領域、２４，３
１…n+型のドレイン領域、２６，３３…ゲート
電極、２７…第１のｎチヤンネルMOSトランジ
スタ、２８…層間絶縁膜、２９′…半導体基部、
３４…第２のｎチヤンネルMOSトランジスタ、
３５…開孔部。
Figure 1 is a plan view showing a conventional three-dimensional MOS integrated circuit, Figure 2 is a sectional view taken along the line - in Figure 1, and Figure 3 is the first MOS transistor in a conventional MOS integrated circuit. V D of the second MOS transistor provided above via an interlayer insulating film
A diagram showing I D characteristics; FIG. 4 is a plan view of a three-dimensional structured MOS integrated circuit showing an embodiment of the present invention;
5 is a cross-sectional view taken along the line --- in FIG. 4, and FIG. 6 is a cross-sectional view taken along the -- line in FIG. 4. 21...p-type semiconductor substrate, 22...field insulating film, 23,30...n + type source region, 24,3
DESCRIPTION OF SYMBOLS 1...n + type drain region, 26, 33...gate electrode, 27 ...first n-channel MOS transistor, 28...interlayer insulating film, 29'...semiconductor base,
34 ...Second n-channel MOS transistor,
35...Opening part.
Claims (1)
設けられたフイールド絶縁膜と、このフイールド
絶縁膜により分離された島状の基板領域に設けら
れた第１のMOSトランジスタと、このMOSトラ
ンジスタを含む基板全面に被覆された層間絶縁膜
と、前記MOSトランジスタの上方に位置する前
記層間絶縁膜部分の上に設けられた第２のMOS
トランジスタとを具備した積層構造のMOS型集
積回路において、前記第２のMOSトランジスタ
のゲート電極が延びる一端部を前記フイールド絶
縁膜に対応する前記層間絶縁膜上に延出させ、か
つ該第２のトランジスタにおける延出部のチヤン
ネル領域下に位置する前記層間絶縁膜及びフイー
ルド絶縁膜の一部にそれら絶縁膜を貫通する開孔
部を穿設すると共に、前記第２のトランジスタの
チヤンネル領域が形成される半導体基部を前記半
導体基板に前記開孔部を通して接続したことを特
徴とするMOS型集積回路。1 A semiconductor substrate of one conductivity type, a field insulating film provided on the surface of this substrate, a first MOS transistor provided in an island-shaped substrate region separated by the field insulating film, and this MOS transistor. an interlayer insulating film covering the entire surface of the substrate, and a second MOS provided on the interlayer insulating film portion located above the MOS transistor.
In a MOS type integrated circuit having a stacked structure and comprising a transistor, one end portion of the second MOS transistor where the gate electrode extends is extended onto the interlayer insulating film corresponding to the field insulating film, and the second MOS transistor An opening that penetrates the interlayer insulating film and the field insulating film located under the channel region of the extension portion of the transistor is formed in a part of the interlayer insulating film and the field insulating film, and a channel region of the second transistor is formed. A MOS type integrated circuit, characterized in that a semiconductor base is connected to the semiconductor substrate through the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56192218A JPS5893372A (en) | 1981-11-30 | 1981-11-30 | Mos-type integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56192218A JPS5893372A (en) | 1981-11-30 | 1981-11-30 | Mos-type integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5893372A JPS5893372A (en) | 1983-06-03 |
| JPS6253951B2 true JPS6253951B2 (en) | 1987-11-12 |
Family
ID=16287621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56192218A Granted JPS5893372A (en) | 1981-11-30 | 1981-11-30 | Mos-type integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893372A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5166091A (en) * | 1991-05-31 | 1992-11-24 | At&T Bell Laboratories | Fabrication method in vertical integration |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56144530A (en) * | 1980-04-10 | 1981-11-10 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1981
- 1981-11-30 JP JP56192218A patent/JPS5893372A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56144530A (en) * | 1980-04-10 | 1981-11-10 | Fujitsu Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5893372A (en) | 1983-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4571609A (en) | Stacked MOS device with means to prevent substrate floating | |
| US5146298A (en) | Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor | |
| US6498370B1 (en) | SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same | |
| TWI284411B (en) | Vertical double-diffused metal oxide semiconductor (VDMOS) device incorporating reverse diode | |
| JPH0357614B2 (en) | ||
| US5811855A (en) | SOI combination body tie | |
| JPS5943829B2 (en) | Complementary field effect transistor integrated circuit device | |
| JPS5816572A (en) | Semiconductor device | |
| CN1223005C (en) | Buried metal contact structure and manufacture of semiconductor FET device | |
| JPS6252469B2 (en) | ||
| JP4852188B2 (en) | Semiconductor device | |
| JPH04216674A (en) | Horizontal-type mos control-type thyristor | |
| JPS6234150B2 (en) | ||
| US4584593A (en) | Insulated-gate field-effect transistor (IGFET) with charge carrier injection | |
| JPS6253951B2 (en) | ||
| JP2825038B2 (en) | Semiconductor device | |
| JPH0241182B2 (en) | ||
| JPS6262069B2 (en) | ||
| JP3217552B2 (en) | Horizontal high voltage semiconductor device | |
| JPH0682840B2 (en) | MOS semiconductor device | |
| JPS6230704B2 (en) | ||
| US20020113266A1 (en) | Semiconductor devices and methods for manufacturing the same | |
| JP3300482B2 (en) | Thyristor with insulated gate | |
| JPH0560266B2 (en) | ||
| JP2680846B2 (en) | Semiconductor memory device |