JPS5835973A - Buried gate type gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To reduce ON-gate currents by forming an N2 cathode layer opposite to the central section of a P2 buried gate layer dispersed and arranged to a P2 base layer in structure in which an opposite P1 anode layer is eliminated through division or without shaping a central section. CONSTITUTION:In a surface gate type GTOSCR having the four-layer structure of P1N1P2N2, the areas of the P2<+> buried gate layers are inhibited within ranges required for drawing out OFF-gate currents, P2<+> layers are not formed at central section (oblique line sections) through which reactive ON-gate currents flow, and an N1 base layer is left just under the central sections without shaping P1 emitter layers, and short-circuited by an anode electrode A. Since the resistance of a P2<+> gate is far lower than that of the P2 base in the structure, the density of the ON-gate currents is increased through the elimination of the P2<+> layer, a reactive section is decreased, and the ON-gate currents can be reduced. The areas of the P2<+> layers are further decreased, a self-diffusion effect is diminished, and gate currents are further reduced. The thyristor does not operate by mistake even in case of turn-OFF because there is no P1 layer just under the section eliminated of the P2<+> buried gate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to buried gate gate turn-off (GTO) thyristor structures.

The buried gate type GTO thyristor is different from the normal surface gate type shown in FIG. 1, as shown in FIG. ! An i II M impurity layer is provided in a distributed manner, and the pt layer is used as a gate layer. The surface gate type GTO thyristor shown in Figure 1 has a cathode
The N2 emitter layer is divided into a short fence-like narrow structure, whereas the buried gate type ()To thyristor has a narrow structure with a short fence-like width.
An N1 emitter layer is formed entirely on the second buried gate layer. This is based on the fact that in the S buried gate type GTO thyristor, the 2E current flows through the gate slit S, and the P1+ buried gate portion does not operate as a thyristor. Therefore, the buried gate type GTO thyristor has the advantage that short circuits between the gate and the cathode are less likely to occur, making it easier to manufacture.

However, in the buried gate type GTO thyristor, the iris does not operate unless the amount corresponding to the Pt buried gate is removed.

As shown in FIG. 3, P! of the on-gate current gt! N in the part where the thyristor does not operate from the gate, and the current component tl flowing from the emitter layer do not contribute to the turn-on operation, that is, the on-gate current gt becomes larger than necessary, and the turn-on current becomes larger than the live current. This will reduce the gain. In order to reduce this process g t /, P
, reducing the buried gate area makes it more likely to cause turn-off failure because the P1+1+ layer operates as a thyristor.The present invention was made in view of the above circumstances, and suppresses the buried gate area to the necessary range. The on-gate current can be reduced by dividing the cathode N1 layer so as to equivalently remove the redundant Pt layer, or by creating a divided structure in which the central part of the Pi layer is not formed and the anode 13 layer facing it is deleted. The purpose of the present invention is to provide a built-in gate type GTO thyristor.

FIG. 4 shows a simple embodiment of the invention. The difference between this figure and Figure 3 is that the area of the P-buried gate layer is within the range necessary to draw the off-gate current, and the Pt layer is placed in the central area (shaded area) where the invalid on-gate current flows. The structure is such that the N1 base layer is left as the N1 base layer without forming the P and emitter layers in the central vertical region, and is short-circuited by the anode electrode.

In this structure, the resistance of the P2fi-containing gate layer is P.

Since it is much smaller than the base resistance, deletion of the P1+ layer increases the current density of the on-gate current. In addition to this, it is possible to reduce the gate current gt, which also reduces the reactive component of the on-gate current.

moreover,? Generally, evitaxial growth is used to form the buried gate layer, but the area reduction of the 12th layer has the effect of reducing autodoping, thereby making the reduction in gt even more effective. Note that the 211477 layer is not formed directly under the deleted portion of the P-buried gate layer, and a transistor is formed.
The thyristor operates only as a thyristor, and does not cause erroneous thyristor operation even when the device is turned off.

In Example 1, the rate of decrease in on-gate current gt could be reduced by about 60% compared to that in FIG.

FIG. 5 shows another embodiment of the invention. The difference between this figure and FIG. 3 is that the N! A single Pt layer is left without forming an emitter layer, and P is connected to one cathode using an insulating film such as an 81 oxide film to prevent short-circuiting of the canned emitter.
The point is that the l-base layer is separated.

This structure reduces the on-gate current reactive component and increases the on-gate current density near the gate slit.
In other words, it can be turned on with less on-gate current. Furthermore, when turning off the device by reverse biasing the N1 emitter, an increase in leakage current due to N1 emitter shorting is prevented.

In this embodiment, the reduction rate of the on-gate current gt can be reduced by about 70% compared to that in Figure 3. In this way, in the present invention, p: from the part of the buried gate that does not contribute to the thyristor operation to N, To create a structure that reduces the current flowing to the emitter layer.

The turn-on gain can be increased by reducing the reactive component of the on-gate current.

[Brief explanation of the drawing]

Figure 1 is a structural diagram of a conventional surface-gate GTO thyristor (
a) and a partially oblique view (b), Fig. 2 is a structural diagram (L) and a partially oblique view (b) of a conventional different gate type GTO thyristor, and Fig. 3 is a conventional buried gate fi GTO thyristor. 4 is a diagram for explaining the on-gate current, FIG. 4 is a structural diagram showing one embodiment of the present invention, and FIG. 5 is a structural diagram showing another embodiment of the present invention. A... Anode electrode, K... Cando electrode, G gate electrode, P1+... Buried gate layer. Figure 1 (a) Figure 2 (a) Figure 2 (b)

Claims (1)

[Claims] ! tlisl't N has a four-layer structure with a high star in the base layer, and the gate layer is opposite to the central part so as to reduce the current flowing from the central part that does not contribute to the thyristor operation to the emitter layer. A buried gate type gate turn-off iris transistor characterized in that the cathode M8 layer has a divided structure, or the anode 11 layer facing the central portion is omitted without forming the central portion.