JPS63224361A - Buried gate gto thyristor - Google Patents
Buried gate gto thyristorInfo
- Publication number
- JPS63224361A JPS63224361A JP5848187A JP5848187A JPS63224361A JP S63224361 A JPS63224361 A JP S63224361A JP 5848187 A JP5848187 A JP 5848187A JP 5848187 A JP5848187 A JP 5848187A JP S63224361 A JPS63224361 A JP S63224361A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- layer
- gate current
- insulating film
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
九産業上の利用分野
本発明は、埋込ゲート層を有するGTO(ゲートターン
オフ)サイリスタに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a GTO (gate turn-off) thyristor with a buried gate layer.
80発明の概要
本発明は、埋込ゲート形GTO+イリスタにおいて、
埋込ゲート層と対向する部分でエミッタ層表面にエミッ
タ電極との間に絶縁膜を形成した構造とすることにより
、
オンゲート電流効率を高くできるようにしたものである
。80 Summary of the Invention The present invention improves on-gate current efficiency by forming an insulating film between the surface of the emitter layer and the emitter electrode in a portion facing the buried gate layer in a buried gate type GTO+iristor. It was designed so that it could be made higher.
C0従来の技術
埋込ゲート層を有するGTOサイリスタは、第2図に示
す構造にされる。PI @ Nl m Pl e N1
の41mを有し、P、ベース層中に格子状や短冊状の高
1mg不純物層P−を埋込み形成し、このPt層をゲー
ト層としてゲート電極G、にオーム接続を得る。P!″
″は低濃度不純物層、Aはアノード電極、Kはカソード
電極、工1は絶縁膜である。C0 Prior Art A GTO thyristor with a buried gate layer is constructed as shown in FIG. PI @ Nl m Pl e N1
A lattice-like or strip-like impurity layer P- with a height of 1 mg is embedded in the Pt base layer, and an ohmic connection is obtained with the gate electrode G using this Pt layer as a gate layer. P! ″
'' is a low concentration impurity layer, A is an anode electrode, K is a cathode electrode, and 1 is an insulating film.
このような構造のGτ0サイリスタは、第3図に示すカ
ソード分割形GTOサイリスタに較べて、ゲートカソー
ド間の絶縁が容易になるし、面積利用率や熱抵抗特性に
優れ、大電力制御用のGTO廿イリスタに多く採用され
ている。Compared to the cathode split type GTO thyristor shown in Fig. 3, the Gτ0 thyristor with such a structure can easily insulate the gate and cathode, has excellent area utilization efficiency and thermal resistance characteristics, and is suitable for GTO thyristors for high power control. It is widely used in Irista.
D0発明が解決しようとする問題点
従来の埋込ゲート形GTOサイリスタにおいて、そのタ
ーンオンゲート電流の利用効率がカソード分割形GTO
サイリスタに較べて劣る問題があった。これを以下に詳
細に説明する。D0 Problems to be Solved by the Invention In the conventional buried gate type GTO thyristor, the utilization efficiency of the turn-on gate current is higher than that of the cathode split type GTO thyristor.
There was a problem that it was inferior to thyristors. This will be explained in detail below.
第2図の綱成において、オンゲート′也流は連結された
埋込ゲート層P1 かり単一のLミッタ層N。In the architecture of FIG. 2, the on-gate flow consists of a connected buried gate layer P1 and a single L-mitter layer N.
に向って矢印で示すように流れる。このとき、ターンオ
ンする実効的なサイリスタ部は、埋込ゲート層P1+の
存在しない投影領域qになり、この投影領域SでのN、
エミツタ層に流れ込むゲート電流のみがオンケート電流
として有効なものになる。It flows as shown by the arrow. At this time, the effective thyristor part that turns on becomes the projection region q where the buried gate layer P1+ does not exist, and in this projection region S, N,
Only the gate current flowing into the emitter layer becomes effective as an on-state current.
即ち、分布ゲート電流成分のうち、N、領域に流れ込む
ゲート電流成分によってN、エミツタ層からの電子の注
入があるも、これは高濃度埋込層p、+でトラップされ
、ベース層からの注入を喚気しない無効成分となる。こ
れに対して、第3図の購成では、上述の無効成分がない
。That is, among the distributed gate current components, electrons are injected from the emitter layer due to the gate current component flowing into the N region, but these are trapped in the heavily doped buried layer p, and are injected from the base layer. It becomes an ineffective ingredient that does not excite. In contrast, the purchase shown in FIG. 3 does not have the above-mentioned ineffective components.
従って、埋込ゲート形GTOサイリスタではゲートター
ンオン電流が分割カンード形GTOサイリスタのそれに
較べて多くなり、ターンオンゲート電流の利用効率が悪
く、ゲート電源やゲート電流制御票子に容量の大きいも
のを用意しなければならない。Therefore, in a buried gate type GTO thyristor, the gate turn-on current is larger than that in a split cand type GTO thyristor, and the turn-on gate current is used less efficiently, and a large capacity gate power supply and gate current control board must be prepared. Must be.
1、問題点’eFjl決するための手段と作用本発明は
、上紀間甥点に鑑みてなされたもので、PNPNの4層
を有しそのベース領域中に高濃度不純物層全形成して該
/ilをゲート層とする埋込ゲート形GTOサイリスタ
において、前記ゲート層に対向する部分でエミッタ)−
表面に該エミッタ電極との間に絶縁膜?形成した構造と
し、埋込ゲート1@からの*流を実効的なせイリスタ部
に流れ易くする。1. Means and operation for solving the problem The present invention was made in view of the above points, and has four layers of PNPN, and a highly concentrated impurity layer is entirely formed in the base region. In a buried gate type GTO thyristor with /il as the gate layer, the emitter is formed in the part facing the gate layer)
Is there an insulating film between the emitter electrode and the surface? This structure allows the flow from the buried gate 1@ to easily flow to the effective iris register section.
F、実tIIfA例 第1図は本発明の一実施例を示す素子vR面囚である。F, real tIIfA example FIG. 1 shows an example of an element vR showing an embodiment of the present invention.
同図が第2図と異なる部分は、高開度不純物層になるP
1+埋込ゲートノ曽に対向するN、ヱミッタ層櫃域表図
に8101等の絶縁暎工!を形成した点にある。この絶
縁膜工8はP、ベース層と同じ幅寸法にされるときには
該P−ベース層形成に使用するマスクパターンを利用し
、絶縁膜工1部分の形成と同時に形成される。The difference between this figure and Figure 2 is that P becomes a high-opening impurity layer.
1 + Insulation work such as 8101 on the N opposite to the buried gate, emitter layer area table diagram! It is at the point where it was formed. When the insulating film 8 is made to have the same width as the P base layer, it is formed simultaneously with the formation of the insulating film 1 using the mask pattern used for forming the P base layer.
上述のような構造によれば、Pt層からのゲート電流は
N、エミツタ層のうちカンード電極にとオーミック接触
する領域(絶縁膜工、が形成されていない領域)に流れ
易くなる。従って、ターンオンするための実効的なせイ
リスタ部でのN、層からの電子の注入を喚起し易くなり
、ゲート電流の利用効率を高くシ、ゲート電流の低減に
なる。According to the above structure, the gate current from the Pt layer easily flows to the region of the N emitter layer that makes ohmic contact with the cando electrode (the region where the insulating film is not formed). Therefore, it becomes easier to inject electrons from the N layer in the effective iris resistor section for turn-on, thereby increasing the gate current utilization efficiency and reducing the gate current.
本実施例に基いた実施例として、第2図の構造のものと
、第1図の構造のものとについて各部を同じ条件にした
ものを試作し、最小オンケート電流を測定すると、本実
施例のものでは約115にまで低減できた。As an example based on this example, we made prototypes with the structure shown in Figure 2 and the structure shown in Figure 1 under the same conditions for each part, and measured the minimum on-state current. We were able to reduce the number to about 115.
なお、実施例では絶縁膜1st”Pt”盾と同じ1鴫寸
法にする場合を示したが、これは限ずしも一致させる必
要はなく、両者が対向する構造である限りにおいてオン
ゲートの電流効率を高める効果がある。In addition, in the example, the case where the size is the same as that of the insulating film 1st "Pt" shield is shown, but this does not necessarily have to be the same, and as long as the two face each other, the on-gate current efficiency will be improved. It has the effect of increasing
G1発明の効果
以上のとおり、本発明はゲート層に対向する部分でエミ
ツタ層表面に絶縁膜を形成した構造としたため、埋込ゲ
ート層のオンゲート電流が実効的サイリスタ部に流れ易
くなり、オンゲート電流の電流効率を良くシ、ゲート″
−4源やゲート電流制御素子の小容鼠化を図ることがで
きる。G1 Effects of the Invention As described above, the present invention has a structure in which an insulating film is formed on the surface of the emitter layer in the part facing the gate layer, so that the on-gate current of the buried gate layer easily flows to the effective thyristor part, and the on-gate current Improve the current efficiency of the gate.
-4 sources and gate current control elements can be made smaller.
第1図は本発明の一実施例を示す曲面図、第2図は従来
の埋込ゲート形GTOサイリスタの断面図、第3図はカ
ンード分割形GTOサイリスタの断面図である。
P? ・・・埋込ゲート層、工、・・・絶縁膜。FIG. 1 is a curved view showing an embodiment of the present invention, FIG. 2 is a sectional view of a conventional buried gate type GTO thyristor, and FIG. 3 is a sectional view of a canned split type GTO thyristor. P? ...buried gate layer, ...insulating film.
Claims (1)
層を形成して該層をゲート層とする埋込ゲート形GTO
サイリスタにおいて、前記ゲート層に対向する部分でエ
ミッタ層表面に該エミッタ電極との間に絶縁膜を形成し
た構造を特徴とする埋込ゲート形GTOサイリスタ。A buried gate type GTO that has four layers of PNPN and has a high concentration impurity layer formed in its base region and uses this layer as a gate layer.
A buried gate type GTO thyristor characterized in that an insulating film is formed on a surface of an emitter layer at a portion facing the gate layer and between the emitter electrode and the emitter electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5848187A JPS63224361A (en) | 1987-03-13 | 1987-03-13 | Buried gate gto thyristor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5848187A JPS63224361A (en) | 1987-03-13 | 1987-03-13 | Buried gate gto thyristor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63224361A true JPS63224361A (en) | 1988-09-19 |
Family
ID=13085622
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5848187A Pending JPS63224361A (en) | 1987-03-13 | 1987-03-13 | Buried gate gto thyristor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63224361A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5591991A (en) * | 1993-07-28 | 1997-01-07 | Ngk Insulators, Ltd. | Semiconductor device and method of manufacturing the same |
-
1987
- 1987-03-13 JP JP5848187A patent/JPS63224361A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5591991A (en) * | 1993-07-28 | 1997-01-07 | Ngk Insulators, Ltd. | Semiconductor device and method of manufacturing the same |
US5739044A (en) * | 1993-07-28 | 1998-04-14 | Ngk Insulators, Ltd. | Method of manufacturing semiconductor device |
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