JPS6364691A - Memory device - Google Patents

Abstract

PURPOSE:To approach an access time and an access cycle to a high speed static (S)-RAM by combining two types of S-RAMs with different access times and comprising a memory bank. CONSTITUTION:When a request data 112 and an address data 100 are simultane ously inputted, the high speed S-RAM1 comprising the memory bank and a normal speed S-RAM2 output read signals 101a, 101b, 101c and 101d correspond ing to respective timing generators 3 and 4 in the S-RAM2 access time t2 longer then the access time t1 and the S-RAM access times t1. Signals 100c and 100d output following signals 100a and 100b through a selector 5. Similarly in writing, the access time and the access cycle approach substantially the high speed S-RAM. Without using only expensive the high speed S-RAM, a high speed action is made accordingly.

Description

[Detailed Description of the Invention] [Industrial Application] The present invention relates to a storage device, and particularly to a storage device including two types of static memory (hereinafter referred to as S-RAM) with different access times. .

[Conventional technology]

BACKGROUND ART High-density integrated semiconductor memory is generally used in storage devices used in data processing systems and the like. In particular, it is widely used in 5-RAM because the access time is short and the data refresh time (necessary for dynamic memory) is small.

By the way, there is always a demand for faster and more efficient processing in data processing systems, etc., and one of the major challenges for storage devices is to shorten the access time and cycle time when writing data and starting. It is. The access time of S-RAM, which is generally used as a storage device, is several times the klovk cycle, and is usually 15n88i. However, in recent storage devices, there is a desire to further shorten access time, and therefore, storage devices using general S-RAMs such as those described above have the disadvantage of long access times.

On the other hand, daytime speed S-RAMri and the above-mentioned general S-RAM
Compared to VC, the access time is half to several minutes, and it can improve the performance of the storage device, but it is expensive and has the disadvantage that it is difficult to reduce the manufacturing cost of the storage device.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention, in other words, the purpose of the present invention is to achieve faster access times and vehicle times than general storage devices by using two types of 5-RAMs with different access times in combination. S-RA
The purpose of the present invention is to provide a storage device that can approach M.

[Means for solving problems]

In the storage device of the present invention, the data is written or read by executing the data transfer n times. or a first timing generator that sends out a first tying signal for performing reading, and m (n
) and input the request signal to write the first static memory bank or! a second timing generator that outputs a second timing signal for performing a second writing or reading operation, and a second timing generator that outputs a second timing signal for performing a second writing or reading operation; The static memory bank is configured to have an access time of (n−m) second static memory banks.

〔Example〕

Hereinafter, a storage device according to the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. h
In the figure, write data 100 of the storage device r'i of the present invention is divided and written into high-speed S-RAMI and 8-RAM 2, and read out as read data 102 as needed.

S-RAMx is composed of two banks #0 and #l. Bank #0 is write signal 1 sent by register 8
00a is written to the address indicated by the address signal 111 (described later) in accordance with the typing signal 114 (described later) K. Similarly, write data 100b sent by bank #1ri register 9 is written to the address indicated by address signal 111 in accordance with timing signal 114.

8-RAM2 consists of two banks #2 and #3. Bank #2 writes the write signal 100c sent by the register 10 to the address indicated by the address signal 111 in accordance with a timing signal 115 (described later). Similarly, bank #3 r! The luxury signal 100d sent by the register 11 is written to the address indicated by the address signal 111 in accordance with the timing signal 115.

Note that the write data 100 is transferred four times from an external processing device, etc., and is manually inputted into registers 8 to 11, respectively, and is sequentially sent out as the above-mentioned write signals 100a to 100d.

Further, address data 11 (H; j) is input to the register 6 and sent out as an address signal 111.

Kirani's request data 112 is manually inputted into the register 7 and piled up as a single request signal 113.

Timing generator 3 and above request signal 11
3, and sends out a timing code 114 that starts the write operation of S-R and AMi.

Similarly, the timing generator let request signal 113 is inputted, and a timing foil number 115 for starting the write operation of the S-RAM 2 is output.

Note that the address signal 1 is applied to the data written to 8-RAMI.
11 and can be sent out as read signals 101a and 101b.

Also, the data written to 5-RAM2 is the address signal 1.
11 and is sent out as recovered signals 101C and 101d.

The selector 5 inputs the above consecutive signals IU1a-11JId, and sequentially outputs the consecutive signals 1 according to the select signal 116.
Send as 01. Further, the register 12rt manually inputs the output number 101 and sends it as A first output data 102 to an external processing device. In this way, the successive data 102 is sent to the outside by four transfers. data 112
and address data 110 are input at the same time, and the write data 100 is transferred four times to write the write signal 1.
00a-100d. Since the timing generator 3 sends the timing signal 114 at the same time as the write signal 100b is sent, the write signals 100a and 100b are simultaneously written to banks #0 and #1 of the S-RAMI, respectively. Following the above, the timing generator 4 outputs the timing signal 115 at the same time as the write signal 100d is sent.
, so banks #2 and #3 of 5-RAM2
Write signals 100C and 100d are simultaneously written to the respective memory cells.

FIG. 2 (bl is a waveform diagram explaining the read operation of the above storage device. In the figure, when request data 112 and address data 110 are input simultaneously, S-RA
Read signals 101a and 101b are sent out after MIrt access time 11. , 5-RAM2ri sends out read signals 101c and 101d after access time t2. Following the above, the selector 5 outputs the select signal 11
6, the above read signals 101a to 101d are sequentially sent out as the read signal 101. At this time, the access time as a storage device is
access time t1 approaches.

In this way, in the above storage device, by incorporating a high-performance 5-RAM into a part of the memory element, it is possible to realize an access time comparable to that of the 5-RAM.

In the above description, a storage device consisting of two speed-limiting 5-RAM banks and two general 5-RAM banks has been described for the case where the number of data transfers is four, but storage devices with other configurations can be implemented in the same manner. For example, high-speed 5-RAM2
8 by bank and general S-RAM 5 bank
A storage device that transfers data once can also be easily realized in the same manner as described above. That is, by increasing the number of data transfers, it is possible to reduce the usage ratio of the high-speed 5-RAM and obtain a memory &t[j whose access time corresponds to a storage device using only the high-speed 5-RAM.

〔Effect of the invention〕

As explained above in detail, according to the storage device of the present invention, a memory bank is configured by combining two types of 5-RAMs with different access times, and data transfer is performed multiple times. The access time of S is fast.
- It has the effect of being able to shorten the access time to a value equivalent to that of RAM. Therefore, the buoy time can be reduced by that much.

In addition, one of the memory elements is made up of high-speed S-RAM, and most of the others are made up of general 5-RAM, so
Another advantage is that a storage device with improved performance can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention, and FIG. 5-RAM, 2...5-RAM
, 3.4・°°...timing generator, 5...
····selector. l' Agent Ben-kunshi Uchihara Plate/Me\ ,・'' (+I Foil 1 Diagram/θθshi ~1trci---↓Kiyoshishishishishishishishishishishishishishishishishishishishishishishishishishishishishishi 2
times ((1)

Claims (1)

[Claims] In a storage device that writes or reads data by executing data transfer n times, a request signal instructing the writing or reading is input, and a first writing or reading is executed. a first timing generator that sends out a first timing signal; m (m<n) first static memory banks that write or read the data according to the first timing signal; a second timing generator that outputs a second timing signal that inputs and performs a second write or read following the write or read of the first static memory bank; 1. A storage device comprising: (n−m) second static memory banks in which data is written or read and whose access time is longer than that of the first static memory bank.