JPH0242700A - Ic memory - Google Patents

Abstract

PURPOSE:To more effectively utilize the high-speed character of the access time of a column address by generating a row line select signal and a column line select signal with individual timings. CONSTITUTION:A row address latch circuit 1 and a column address latch circuit 3 are individually provided to a static RAM, and an address signal in each address latch circuit 3 is latched by a difference lock signal. For such a reason, the respective access time characteristics of the row address and column address are effectively utilized. Thus, a high-speed memory system can be constructed, and simultaneously contributed to the performance improvement of the memory system, can be executed.

Description

[Detailed Description of the Invention] [Summary] Regarding the memory cell selection method in a static RAM in which memory cells are arranged in a matrix and has a built-in address latch circuit, a latch circuit for human input signals is incorporated in order to increase the speed. In order to further improve the access time of static RAM, in a static RAM with a built-in address latch circuit, a word address latch circuit and a digit address latch circuit are individually provided, and the address signal in each address latch circuit is It is configured to latch using different clock signals.

[Industrial application field]

The present invention relates to a static RAM with a built-in address launch circuit among semiconductor memory devices, and in particular, a memory cell selection method suitable for use in cases where high-speed read access is strongly required, such as when used as a cache memory. The present invention relates to an IC memory having the following features.

[Conventional technology]

With the recent demand for faster computer systems, there is a demand for faster access times for memory devices.

However, when accessing data in a conventional memory device, as shown in the time chart of FIG.
), data could not be written using a write signal unless all of the requirements were met. As a result, even if the RAM originally has a high access time, it is unable to achieve sufficient performance, and it has been necessary to design a memory circuit with redundant cycle time.

In order to solve the above-mentioned problems, static RAMs have recently been developed in which a latch circuit for human input signals or human output signals is built into the RAM chip. This R
By using AM, the user need only satisfy the set-up/hold time for the clock of the manually operated signal latch circuit without being aware of the set-up and hold regulations between each signal as described above.

Moreover, the set-up/hold time regulations for this clock are the same for chip select signals, address signals, data input signals, and write signals, and system designers are allowed to use this clock at the minimum cycle time. It will be done. Also, inside the RAM, this latched signal is used to generate the optimal set-up/hold time by itself to create an access signal for each memory cell of the RAM, and the optimally trimmed signal is used to access the RA.
It becomes possible to operate M. FIG. 3 shows a conventional static RAM with a built-in latch circuit developed based on such a technical idea.

In the figure, 50 is an address latch circuit that latches an address signal, 51 is a row decoder that converts the address signal into a word (hereinafter also referred to as row) address, and 5
2 is a column decoder that converts the address signal into a digit (hereinafter also referred to as column) address; 53 is a memory cell array accessed by each address signal; and 54 is a column decoder that temporarily converts data output to the memory cell 53 55 is a write signal latch that latches a data write signal, and 56 is a chip select latch that latches a chip select signal.

In the figure, according to latch clock synchronization, a chip select signal, an address signal, and a write signal are transmitted to a chip select latch circuit 56 and an address latch circuit 50, respectively.
, the address signal latched by the write signal latch circuit 55 and the address signal latched by the address latch circuit 50 is sent to the memory cell array 53 by the row decoder 51 and column coder 52.
The memory cell is converted into a row address and a column address corresponding to the address signal in the memory cell, the memory cell is accessed at the same timing, and data manually input from the human output huffer 54 is written in accordance with the write signal.

[Problem to be solved by the invention]

As described above, the conventional static RAM with a built-in latch circuit uses the same clock signal to latch the address signal into the address latch circuit, and then converts it into a row address and a column address using the row address decoder and column address decoder. , the row address and column address of a memory cell are accessed, but in the case of a static RAM in the shell, the access time from the column address is faster than the access time from the row address. The reason for this is that when the row address changes as shown in FIG. 5, it takes a long time for the data on the bit line to invert from 0 to 1 or 1-0. On the other hand, when the column address changes, if the row address is fixed, the data on the bit line has already been determined, so the only time required is to select which bit line, so the access time from the column address is faster. Become.

Viewed from the address access characteristics of static RAM, accessing the row address and column address at the same timing as in the past does not allow full use of the high-speed column address access function. Overall, there was a problem in that speeding up memory access time was limited.

The present invention has been made to solve the above-mentioned problems, and its purpose is to obtain a static RAM with a built-in address latch circuit that makes full use of the characteristics of column address access and can be expected to operate at higher speeds. do.

[Means to solve the problem]

According to the invention, the above objects are achieved by the means specified in the claims. That is, the present invention provides a static RAM that can incorporate an address latch circuit.
A row address latch circuit and a column address latch circuit are individually provided, and the address signal in each address latch circuit is latched using a different clock signal.

[For production]

According to the IC memory according to the present invention, static RAM
A row address latch circuit and a column address latch circuit are separately provided for the memory cell array, and each address latch circuit latches a row address signal and a column address signal using different clocks, and then each address signal is sent to a row decoder, The column decoder is configured to manually generate the row line select signal and column line select signal for accessing the corresponding memory cell at individual timings, which makes more effective use of the high speed access time of column addresses. obtain.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention, in which l is a row address latch circuit that latches a row address signal in response to a clock 1, 2 is a row decoder that converts the row address signal into a row line select signal, 3 is clock 2
4 is a column decoder that converts the column address signal into a column line select signal, 5 is a memory cell array, 6 is a write signal latch circuit that latches a line signal, and 7 is a chip select signal. 8 is an input/output buffer that outputs data to the memory cell array 5.

Next, the operation of this embodiment based on the above configuration will be explained with reference to the time chart shown in FIG.

First, when the memory cell array 5 is accessed from a row address by the clock 1 and data is output from the human output buffer 8, the row address signal is input to the row address latch circuit 1 and latched by the clock 1, and then the row decoder When the row address is accessed by converting it into a row line select signal in 51, when the row address changes as described above, the data on the bit line takes a long time to invert from 0 to 1, so the access time 1 elapses. After that, the data will be output.

On the other hand, when the row address is fixed and data is output by changing the column address, the column address signal is latched into the column address latch circuit 3 by the clock 2, and converted into a column line select signal by the column decoder 4. Access column address. in this case,
Since the row address is fixed and the data on the bit line has already been determined, the only time required is to select which bit line, so the data output time is access time 2. This shows that data can be output immediately after the clock signal is input, compared to the case of accessing from the row address.

〔Effect of the invention〕

As explained above, the method of the present invention uses static R
The AM is provided with separate row address latch circuits and column address latch circuits, and the address signals in each address latch circuit can be latched by separate clock signals, so the access time characteristics of each row address and column address are effective. By using this method, it is possible to construct a high-speed memory system, and there is an advantage that it can contribute to improving the performance of the memory system.

4,

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the embodiment, and FIG. 3 is a diagram showing the function of a conventional static RAM with a built-in address latch circuit.
FIGS. 4 and 5 are time charts explaining the operation of a general static RAM.

Claims (1)

[Claims] An IC memory characterized in that, in a static RAM having a built-in address latch circuit, a word address latch circuit and a digit address latch circuit are individually provided, and address signals in each address latch circuit are latched with different clock signals.