JPS6364128A - 8085 microcomputer - Google Patents

Abstract

PURPOSE:To artificially execute the modification to an address designated with a register pair by adding and subtracting the value of an external register to the address outputted by a CPU and making it into a new address when a writing instruction is executed. CONSTITUTION:First, a displacement value is written into a register circuit 3. The circuit 3 outputs a signal 13 to show that writing is executed and activates a memory writing cycle detecting circuit 4. The circuit 4 detects a writing cycle when a CPU 1 executes a next instruction, activates an address adding circuit 6 and outputs a signal 14 to prohibit an address buffer 9. The circuit 6 adds an HL register pair value outputted by the CPU 1 and the displacement value of the circuit 3 and outputs them to an address bus 12. At this time, since the buffer 9 is prohibited, the value before adding outputted by the CPU 1 is not outputted onto the bus 12. On the other hand, an accumulator value is outputted onto the data bus 11, and written into the address modified by a memory writing signal from a control signal generating circuit 2.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to an 8085 microcomputer.

(Prior art) Conventionally, 8085 microcomputers have an addressing method called register indirect addressing, and addresses can be specified using register bear IIL, BC, DE, or Intex addressing of 280 microcomputers. As in , it was not possible to specify an address by adding or subtracting an arbitrary value called displacement to the value of the register bear for address specification.

In memory write using register indirect addressing in the 8085 microcomputer, the instruction code is fetched in the first machine cycle (instruction code fetch cycle), and the accumulator or register value is written to the address indicated by the register bear in the next machine cycle (memory light cycle). - As an example, the mnemonic for the microcomputer 8085 is the instruction rMOVM, ^j, that is, the case where the contents of the accumulator are stored in the address indicated by the HL register bear is as follows.

In the instruction code fetch cycle, the CPU reads the instruction code 77H of the instructions ryov M, AJ from the ROM, and in the next memory write cycle, the CPU outputs the address indicated by the HL register bear on the address bus,
The address on the RAM selected by the address decoding circuit is specified. At this time, the contents of the accumulator are output to the data bus, and by manually controlling the control output of CPU 1, the memory write signal output from the control signal circuit that generates 107M R/W (no. The value on the data bus is written to the address.

(Problems to be Solved by the Invention) The conventional 8085 microcomputer circuit described above has the following problems:
Since it is not possible to specify an address by adding or subtracting a displacement to the value of a register bare, the instructions are poorer than that of a 280 microcomputer, and the software may be sloppy.

SUMMARY OF THE INVENTION An object of the present invention is to provide an 8085 microcomputer circuit that can write a displacement of an arbitrary value to an external register and modify an address designated by a register bear in a pseudo manner.

[Means for solving problems]

The 8085 microcomputer of the present invention is capable of displacing any value of up to 16 bits by assigning it to a fixed I/O or memory address of the CPU.
a register circuit that outputs a signal indicating that displacement writing has been performed;
A memory write cycle detection circuit detects a memory write cycle when an instruction is executed immediately after the CPU writes displacement to the register circuit, and the displacement is activated by the detection signal of the memory write cycle detection circuit and stored in the register circuit. It is characterized by having an address addition circuit that adds the address accessed by the CPU to the address accessed by the CPU.

In this way, when a display current of an arbitrary value is written to an external register circuit and the CPU executes a write instruction using register indirect addressing immediately after writing, the
By adding or subtracting the value of the external register to the address output by the PU to obtain a new address, the address specified by the register bear can be modified with a pseudo displacement.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the 8085 microcomputer circuit of the present invention.

The control signal generation circuit 2 inputs the control outputs of 8085 CPt1l's 10/Grave, Punishment, ■, So, and SH, and combines them in the logic circuit to perform memory write, memory read,
■Generates control signals such as 0 read and IO write. The address latch lO is the A that the cpu t outputs.
In response to the LE signal, the CPU 1 latches the 8-bit data ADo~8 which is output onto the data bus 11.

The address bus buffer 9 inputs the outputs of 8 to AIS and the address latch 10 to the 8-bit address output of cput, and uses the enable input to input the address bus 22.
Output on top. Address decode circuit 5 inputs the address signal on address bus 12 and outputs a selection signal.

ROM7 and ROM8 each use the output of the address decoding circuit 5 as a shoulder input, the output of the control signal generation circuit 2 as an R/W control input, and the address input and data input are connected to the address bus 12 and data bus +1, respectively. . The register circuit 3 receives the output of the address decode circuit 5 as a GE input, and uses the output of the control signal generation circuit 2 as an R/W control input. Register circuit 3 is CPU
The displacement specified by I10 or the memory address is written from the data bus 21 in the memory write cycle by using the content of the register bear accessed by the CPU as a pseudo index. A signal 23 indicating that writing has been performed is output. The address addition circuit 6 uses the output of the register circuit 3 as a first input, and uses the contents of the register bare accessed by the CPU as a second input.
When the enable force 14 is active, the first. The sum of the second inputs is output onto the address bus 12. The memory write cycle detection circuit 4 is CPU tO system (wholesale output So, S
, , R.D.

WR, 10/M is input, and the memory write cycle of the next instruction in which the displacement value is written to the register circuit 3 is executed by inputting the signal 13 indicating that writing to the register circuit 3 has not been performed as a strobe input. Detect and signal 14
Output. The signal 14 is input to the address adder circuit 6 and the enable terminal of the address bus buffer 9 (the enable terminal of the address bus buffer 9 is the inactive terminal r), respectively. Further, the signal 14 is input to the reset terminal of the register circuit 3, and the signal 13 is reset at the edge of the signal 14 changing from active to inactive.

Next, the operation of this embodiment will be explained.

In this embodiment, by writing a displacement value to the register circuit 3 immediately before an instruction that uses register indirect addressing, the CPU writes the displacement value to the register circuit 3 at the address indicated by the register bear when executing the next write instruction using register indirect addressing. The address obtained by adding (or subtracting) the written value can be accessed, allowing address specification similar to index addressing.

Here, the case of the instructions rMOVM, AJ will be explained as an example. First, a displacement value is written into the register circuit 3. This writing is performed using a normal IO write or memory write method. When the displacement value is written to the register circuit 3, a signal 13 indicating that writing has been performed is sent to the memory write cycle detection circuit 4.
is output for. Memory write cycle detection circuit 4
is activated by the output 13 of the register circuit and CPI
II detects a memory write cycle when executing the next instruction rMOVM, AJ, activates the address adder circuit 6, and simultaneously outputs a signal 14 for disabling the address bus buffer 9. Now, CPLI t is the instruction rMO
V.M.

^” In the memory write cycle during execution, the address bus! The address indicated by the register bear HL is output to the memory write cycle detection circuit 4, and the above-mentioned signal 14 is output from the memory write cycle detection circuit 4. The address adder circuit 6 uses the signal 14
The HL register bare value outputted by the CPU 1 and the displacement value written in the register circuit 3 are added together and output onto the address bus 12. That is, CPt11 goes high and the address indicated by the register bear is accessed by modifying the value written in the register circuit 3. At this time, the address bus buffer 9 is inhibited by the signal 14, and the value output by the CPU 1 (value not modified by the adder circuit) is not output onto the address bus 12, so that no data collision occurs. On the other hand, the data bus
The accumulator value is outputted to the top, and is written to the modified address described above by the memory write signal generated by the control signal generation circuit 2. When writing is completed, the output 14 of the memory write cycle detection circuit 4 returns to inactive state, but at the point of change, the output 13 of the register circuit 3 is reset.

(Effect of the invention) As explained above, the present invention allows arbitrary values (
When the CPU executes a write instruction using register indirect addressing immediately after writing, the value of the above external register is added to the address output by the CPU to create a new address, thereby creating a pseudo register bear. It is possible to apply displacement modification to a specified address, and it has the effect of adding an index addressing function that is not available in the 8085 microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the 8085 microcomputer circuit of the present invention. 1...8085CPLl. 2... Control signal generation circuit, 3... Register circuit, 4... Memory write cycle detection circuit, 5... Address decoding circuit, 6... Address addition circuit, 7... ROM,
8...RAM, 9...Address bus buffer, lO...Address latch, 11...Data bus, 12...Address bus, 13...Displacement writing has been performed. Signal, 14... Detection signal of the memory write cycle detection circuit.

Claims (1)

[Scope of Claims] In the 8085 microcomputer, a displacement of an arbitrary value of up to 16 bits is stored by the CPU operation, which is assigned to a fixed I/O or memory address of the CPU, and the displacement is written. A register circuit that outputs a signal indicating that a displacement has been written to the register circuit, a memory write cycle detection circuit that detects a memory write cycle when an instruction is executed immediately after the CPU writes displacement to the register circuit, and activation of the memory write cycle detection circuit. An 8085 microcomputer characterized by having an address addition circuit that is activated by a signal and adds a displacement stored in a register circuit to an address accessed by a CPU.