JPH03269626A - Microprocessor - Google Patents

Abstract

PURPOSE:To shorten the time necessary for prefetch of an instruction by providing two buses for fetch and execution of instructions, a control timing generation circuit, and a control unit for the control timing generation circuit and then switching the driving bus timing. CONSTITUTION:An instruction executing unit 2 executes the instruction taken out of an instruction queue 3. A bus control unit 4 decides an external bus cycle to be executed next based on the states of the queue 3 and the unit 2, and generates a control signal. A normal bus cycle generating circuit 5 produces a bus cycle needed for the unit 2 to execute an instruction and then drives a bus. An instruction fetch bus cycle generating circuit 6 generates an instruction fetch bus cycle when the queue 3 includes an idle area and drives the bus. Then a data selector 7 receives a control signal from the unit 4 and performs a switching operation so as to make the circuit 5 or 6 enable to drive the bus. In this case, the unit 4 controls the circuit 5 so as to satisfy the queue 3 and generates a bus cycle in accordance with the depth of the queue 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor with an instruction prefetch queue.

[Conventional technology]

Conventionally, in this type of microprocessor, the read cycle activated by a brief fetch and the read cycle activated by instruction execution are the same. In this type of microprocessor, if the average execution time of several consecutively executed instructions exceeds the time required to pre-fetch the instruction code of each instruction, the instruction execution unit can execute one instruction. When the execution of the instruction code is completed, the next executable instruction code is available in the queue.

For this reason, external memory (in which instruction codes are written)
This allows the instruction fetch time from the instruction execution time to be excluded from the instruction execution time. As a result, a microprocessor with a queue has the effect of improving processing speed compared to a type that fetches and executes each instruction.

[Problem to be solved by the invention]

In the conventional technology described above, the instruction queue is generally cleared by a jump instruction, etc., and at the jump destination, a brief fetch is executed to a new instruction queue. Therefore, in software that uses many jump instructions, the instruction queue is cleared by this instruction queue. The disadvantage is that the effect of executing briefetch is halved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor that eliminates these drawbacks and can perform high-speed access by having a circuit that generates another bus cycle during briefetch.

[Means to solve the problem]

The configuration of the microprocessor of the present invention includes an instruction queue for taking in instructions fetched for instruction execution, an instruction execution unit for sequentially executing the instructions taken into the instruction queue, and an instruction execution unit for taking instructions into the instruction queue. As a memory read bus cycle when reading the memory, I
a bus cycle generation circuit that starts a bus cycle different from the bus cycle of the lo read or write cycle;
The present invention is characterized by comprising a control circuit that controls the bus cycle generation circuit.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The data selector 1 performs input/output with an external bus. Further, the instruction queue 3 sends out instructions inputted and outputted by the data selector 1 to the instruction execution unit 2 . The instruction execution unit 2 executes the instruction taken out from the instruction queue 3.

Further, the bus control unit 4 determines the next external bus cycle to be executed based on the states of the instruction queue 3 and the instruction execution unit 2, and generates a control signal. Generates the bus cycles necessary for the process and drives the bus. The instruction fetch bus cycle generation circuit 6 generates an instruction fetch bus cycle when there is space in the instruction queue 3,
Drive the bus. Further, the data selector 7 receives a control signal from the bus control unit 4 and performs switching so that either the normal bus cycle generation circuit 5 or the instruction fetch bus cycle generation circuit 6 can drive the bus.

In this embodiment, the bus control unit 4 first controls the normal bus cycle generation circuit 5 to fill the instruction queue 3, and generates bus cycles according to the depth of the instruction queue 3.

Here, the bus timing generated by the instruction fetch bus cycle generation circuit 6 is different from the bus timing generated by the normal bus cycle generation circuit 5, and is performed according to the cycle shown in FIG.

This cycle corresponds to a read cycle in static column mode in a general-purpose dynamic RAM. This static column mode is a mode in which data within the same row address is accessed at high speed. In other words, in a cycle in which the memory reads in response to a brifetch, the address may always be simply incremented or decremented, and therefore data within the same row address may be read.

Therefore, when a fetch is started from address N, the static column mode in the general-purpose dynamic RAM can be used from address N+1 onwards, and a faster fetch cycle can be executed.

The read cycle in this static column mode is about 1/2 of the normal read cycle.Secondly, when the instruction queue is filled, the bus control unit 4 disables the instruction fetch bus cycle generation circuit 6, The bus cycle generation circuit 5 is enabled to generate bus cycles that occur as instructions are executed.

- As an example, in a 1 megabit general-purpose dynamic RAM, the row address and column address are each 10 bits (Ao to A9). At this time, the second
In the figure, for example, the fetch address is 800008
(displayed in hexadecimal), the row address and column address are 200H and 0OOH, respectively, and if input in this order, the second fetch cycle will change the column address to +IH.
This makes it extremely easy to use static column mode.

〔Effect of the invention〕

As explained above, the present invention has two buses, one for fetching an instruction and one for executing an instruction, a timing generation circuit that generates control timing, and a unit that controls it, and by switching the bus timing to drive, Even if a program is created in which the data is cleared frequently, the time required for fetching instructions can be significantly reduced. In addition, access within the same row address becomes possible, and the activated memory access signal (7. rT in general-purpose dynamic RAM) is activated and activated for -degree fetch.
By being able to keep y) active until the fetch is completed, it is possible to eliminate the transient current that occurs during access (flowing at the rise and fall of rry), making it possible to construct a memory system with lower power consumption. .

The figure is a timing diagram illustrating the operation of the general-purpose dynamic RAM in conjunction with FIG. 1.

1...Data selector, 2...Instruction execution unit,
3... Instruction queue 4... Bus control unit, 5...
...Normal bus cycle generation circuit, 6.Instruction fetch bus cycle generation circuit, 7.Data selector.

Claims (1)

[Claims] An instruction queue for fetching instructions for instruction execution, an instruction execution unit for sequentially executing the instructions fetched into this instruction queue, and a memory read bus cycle when fetching instructions into the instruction queue. , a bus cycle generation circuit that starts a bus cycle different from a bus cycle of a memory or I/O read or write cycle associated with instruction execution, and a control circuit that controls this bus cycle generation circuit. A microprocessor characterized by: