JPS6362353A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6362353A
JPS6362353A JP20726686A JP20726686A JPS6362353A JP S6362353 A JPS6362353 A JP S6362353A JP 20726686 A JP20726686 A JP 20726686A JP 20726686 A JP20726686 A JP 20726686A JP S6362353 A JPS6362353 A JP S6362353A
Authority
JP
Japan
Prior art keywords
film
silicon oxide
oxide film
pattern
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20726686A
Other languages
Japanese (ja)
Inventor
Keiji Hirose
啓二 広瀬
Mitsuhiro Matsumoto
充博 松本
Akihiko Osakabe
刑部 昭彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP20726686A priority Critical patent/JPS6362353A/en
Publication of JPS6362353A publication Critical patent/JPS6362353A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent wire breakdown when a contact electrode is formed on an electrode hole, by forming the electrode hole in two steps, in which a hole is provided in a second silicon oxide film with the first pattern of a photoresist film and a hole is provided in a phosphorus glass film and in a first silicon oxide film with the second pattern of the photoresist film. CONSTITUTION: On a semiconductor substrate 21, a first silicon oxide film 22, a phosphorus glass film 23 and a second silicon oxide film 24 are formed. A first etching hole 26 is formed in the second silicon oxdie film 24 by a photoetching method using the first pattern of a photoresist film 25. Thereafter, a second etching bole 27 is formed in the phosphorus glass film 23 and the first silicon oxide film 22 by a photoetching method using the second pattern of a photoresist film 25'. Then the cross sectional area of an electrode hole becomes gradually large toward the outlet from the bottom part. A metal film 28 is formed on the electrode hole and the three films. The three films in the vicinity of the outlet of the electrode hole have obtuse angle. Therefore, wire breakdown does not occur.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置にシリコン酸化膜と燐ガラス膜そ
してシリコン酸化膜とからなる三重膜を具備する半導体
装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which the semiconductor device is provided with a triple layer consisting of a silicon oxide film, a phosphorous glass film, and a silicon oxide film.

従来の技術 半導体装置の三重膜は、化学反応を利用した薄膜の堆積
技術が発展し活用されるようになってきた。ところが三
重膜に、電極形成用の穴をエツチングにより形成する際
、燐ガラス膜とシリコン酸化膜とのエツチング速度の大
幅な相違から、エツチングにより形成した電極穴の断面
は、第3図に示すように、最上層のシリコン酸化膜がひ
さし状にせり出した形状となる。この形状になると、そ
の後で蒸着法により形成する電極配線が断線を生じるの
である。第3図で1は半導体基板、2は第1のシリコン
酸化膜、3は燐ガラス膜、4は第2のシリコン酸化膜、
5は電極穴、6は電極(配線)用金属膜である。
BACKGROUND OF THE INVENTION With the development of thin film deposition technology using chemical reactions, triple-layered films for semiconductor devices have come into use. However, when forming holes for forming electrodes in the triple layer film by etching, due to the large difference in etching speed between the phosphorous glass film and the silicon oxide film, the cross section of the electrode holes formed by etching was as shown in Figure 3. The top layer of silicon oxide film protrudes like an eave. If this shape is adopted, the electrode wiring formed by the vapor deposition method will be disconnected. In FIG. 3, 1 is a semiconductor substrate, 2 is a first silicon oxide film, 3 is a phosphorous glass film, 4 is a second silicon oxide film,
5 is an electrode hole, and 6 is a metal film for electrode (wiring).

発明が解決しようとする問題点 本発明の目的は上述した断線の生じない改良された半導
体装置の製造方法を提供することにある。
Problems to be Solved by the Invention An object of the present invention is to provide an improved method for manufacturing a semiconductor device that does not cause the above-mentioned disconnection.

問題点を解決するための手段 本発明は、半導体基板表面上に第1のシリコン酸化膜、
燐ガラス膜および第2のシリコン酸化膜を順次形成する
工程と、前記第2のシリコン酸化膜上にホトレジスト膜
の第1のパターンを形成し、同パターンにしたがい、前
記第2のシリコン酸化膜を選択的に除去して前記燐ガラ
ス膜を露出する工程と、露出した前記燐ガラス膜上にホ
トレジスト膜の第2のパターンを形成し、同パターンに
したがい、前記燐ガラス膜および第1のシリコン酸化膜
を選択的に除去して前記半導体基板表面を露出させて電
極穴を形成する工程と前記第2のシリコン酸化膜、前記
燐ガラス膜の選択された表面部分上および前記電極穴に
より露出した前記半導体基板表面上に金属膜を形成する
工程とを具備することを特徴とする半導体装置の製造方
法である。
Means for Solving the Problems The present invention provides a first silicon oxide film on the surface of a semiconductor substrate,
a step of sequentially forming a phosphorous glass film and a second silicon oxide film, forming a first pattern of a photoresist film on the second silicon oxide film, and forming the second silicon oxide film according to the same pattern; selectively removing the phosphorous glass film to expose the phosphorus glass film, forming a second pattern of a photoresist film on the exposed phosphorus glass film, and following the same pattern, removing the phosphorus glass film and the first silicon oxide film; selectively removing a film to expose the surface of the semiconductor substrate to form an electrode hole; A method for manufacturing a semiconductor device, comprising a step of forming a metal film on a surface of a semiconductor substrate.

作用 本発明によると、電極穴を、まず、ホトレジスト膜の第
1のパターンによって第2のシリコン酸化膜への開口過
程、ついで、ホトレジスト膜の第2のパターンによって
燐ガラス膜および第1のシリコン酸化膜への開口過程の
二段階で形成するので、同電極穴の側面傾斜が緩和され
、この電極穴上に接触電極を形成したときの断線がなく
なる。
According to the present invention, the electrode hole is first opened in the second silicon oxide film by the first pattern of the photoresist film, and then the electrode hole is opened in the phosphorous glass film and the first silicon oxide film by the second pattern of the photoresist film. Since it is formed in two steps during the process of opening into the membrane, the side slope of the electrode hole is relaxed, and there is no disconnection when a contact electrode is formed on this electrode hole.

実施例 以下、添付図面に示す実施例により、本発明の詳細な説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

第1図は本発明実施によって形成されたPn接合を有す
る半導体装置の断面図であり、第2図a、bはその製造
工程を図示した工程断面図である。本発明の実施に当っ
ては、まず第2図aのように、所定のPn接合を形成し
たシリコンなどからなる半導体基板21の上に第1のシ
リコン酸化膜22.燐ガラス膜23.第2のシリコン酸
化膜24を準備する。これらの膜の形成は、たとえば熱
酸化法、スパッタリング法、化学気相沈着法(CVD法
)、蒸着法等の従来周知の方法によって行なわれる。こ
の第2のシリコン酸化膜24に、ホトレジスト膜25に
よる第1のパターンを用いた周知のホトエツチング法に
より、第一のエツチング開口26を形成する。その後第
2図すのように、燐ガラス膜23.第1のシリコン酸化
膜22に対し、ホトレジスト膜25′による第2のパタ
ーンを用いて、周知のホトエツチング法により、第二の
エツチング開口27を形成する。これによって第一のエ
ツチング開口26および第二のエツチング開口27から
なる電極穴は、底部から出口に向って断面積が次第に大
きくなる、いわゆる、すりばち形状となる。しかる後、
この電極穴および三Mgl上の選択された個所に、たと
えば蒸着法により、電極用金属膜28を形成することに
より、第1図示の半導体装置が形成される。金属膜28
は電極穴の出口付近の三重膜が鈍角になっているため、
断線のおそれがなくなる。
FIG. 1 is a sectional view of a semiconductor device having a Pn junction formed according to the present invention, and FIGS. 2a and 2b are process sectional views illustrating the manufacturing process thereof. In carrying out the present invention, first, as shown in FIG. 2a, a first silicon oxide film 22. Phosphorous glass film 23. A second silicon oxide film 24 is prepared. These films are formed by conventionally known methods such as thermal oxidation, sputtering, chemical vapor deposition (CVD), and vapor deposition. A first etching opening 26 is formed in this second silicon oxide film 24 by a well-known photoetching method using a first pattern of a photoresist film 25. Thereafter, as shown in FIG. 2, the phosphor glass film 23. A second etching opening 27 is formed in the first silicon oxide film 22 by a well-known photoetching method using a second pattern of a photoresist film 25'. As a result, the electrode hole consisting of the first etching opening 26 and the second etching opening 27 has a so-called pincer shape in which the cross-sectional area gradually increases from the bottom toward the exit. After that,
The semiconductor device shown in the first figure is formed by forming an electrode metal film 28 in the electrode holes and selected locations on the three Mgl by, for example, vapor deposition. Metal film 28
Because the triple membrane near the exit of the electrode hole has an obtuse angle,
There is no risk of wire breakage.

本実施例によれば工程が増加して不利のように見えるが
、配線の断線を大幅に低減できることから全体としてみ
れば、工程の増加は問題にならない。
According to this embodiment, the number of steps is increased, which may seem disadvantageous, but the increase in the number of steps does not pose a problem as a whole, since disconnections in wiring can be significantly reduced.

発明の効果 本発明によれば、三重膜構造の絶縁被膜に対して電極穴
を形成する際、まず、最上層の第2のシリコン酸化膜に
対して、ホトレジスト膜の第1のパターンを用いて、径
大な第一のエツチング開口を形成し、ついで、次層の燐
ガラス膜上にホトレジスト膜の第2のパターンを用いて
、同燐ガラス膜および最下層の第1のシリコン酸化膜に
対して、径小な第二のエツチング開口を形成するので、
その電極穴は、側面傾斜のゆるやかなすりばち状になり
、したがって、同電極穴に接触電極を形成したときの開
口上面における断線がなくなり、半導体装置の製造性な
らびに品質の向上が達成される。
Effects of the Invention According to the present invention, when forming an electrode hole in an insulating film having a triple-layer structure, first, a first pattern of a photoresist film is applied to the second silicon oxide film as the uppermost layer. , a first etching opening with a large diameter is formed, and then a second pattern of a photoresist film is formed on the phosphorous glass film as the next layer and the first silicon oxide film as the bottom layer. Then, a second etched opening with a smaller diameter is formed.
The electrode hole is in the shape of a dovetail with a gently sloped side surface. Therefore, when a contact electrode is formed in the electrode hole, there is no disconnection at the upper surface of the opening, thereby improving the manufacturability and quality of the semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施によって形成された半導体装置の
断面図、第2図a、bはその製造工程の工程順断面図、
第3図は従来例半導体装置の断面図である。 21・・・・・・半導体基板、22・・・・・・第1の
シリコン酸化膜、23・・・・・・燐ガラス膜、24・
・・・・・第2のシリコン酸化膜、25.25’・・・
・・・ホトレジスト膜、26・・・・・・第一の開口、
27・・・・・・第二の開口、28・・・・・・電極用
金属膜。 代理人の氏名 弁理士 中尾敏男 ほか1名第1図
FIG. 1 is a sectional view of a semiconductor device formed by implementing the present invention, FIGS. 2a and 2b are sectional views in order of the manufacturing process thereof,
FIG. 3 is a sectional view of a conventional semiconductor device. 21... Semiconductor substrate, 22... First silicon oxide film, 23... Phosphorus glass film, 24...
...Second silicon oxide film, 25.25'...
...Photoresist film, 26...First opening,
27...Second opening, 28...Metal film for electrode. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表面上に第1のシリコン酸化膜、燐ガラス膜
および第2のシリコン酸化膜を順次形成する工程と、前
記第2のシリコン酸化膜上にホトレジスト膜の第1のパ
ターンを形成し、同パターンにしたがい、前記第2のシ
リコン酸化膜を選択的に除去して前記燐ガラス膜を露出
する工程と、前記第2のシリコン酸化膜上および露出し
た前記燐ガラス膜上にホトレジスト膜の第2のパターン
を形成し、同パターンにしたがい、前記燐ガラス膜およ
び第1のシリコン酸化膜を選択的に除去して前記半導体
基板表面を露出させて電極穴を形成する工程と前記第2
のシリコン酸化膜、前記燐ガラス膜の選択された表面部
分上および前記電極穴により露出した前記半導体基板表
面上に金属膜を形成する工程とを具備することを特徴と
する半導体装置の製造方法。
a step of sequentially forming a first silicon oxide film, a phosphorous glass film, and a second silicon oxide film on the surface of the semiconductor substrate; forming a first pattern of a photoresist film on the second silicon oxide film; selectively removing the second silicon oxide film to expose the phosphorous glass film according to the pattern; forming a second photoresist film on the second silicon oxide film and the exposed phosphorous glass film; forming a pattern, and selectively removing the phosphorous glass film and the first silicon oxide film to expose the semiconductor substrate surface and forming an electrode hole according to the pattern;
a silicon oxide film, a metal film on a selected surface portion of the phosphorous glass film, and on the surface of the semiconductor substrate exposed by the electrode hole.
JP20726686A 1986-09-03 1986-09-03 Manufacture of semiconductor device Pending JPS6362353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20726686A JPS6362353A (en) 1986-09-03 1986-09-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20726686A JPS6362353A (en) 1986-09-03 1986-09-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6362353A true JPS6362353A (en) 1988-03-18

Family

ID=16536945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20726686A Pending JPS6362353A (en) 1986-09-03 1986-09-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6362353A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164530A (en) * 1980-05-22 1981-12-17 Sanyo Electric Co Ltd Formation of contacting hole of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164530A (en) * 1980-05-22 1981-12-17 Sanyo Electric Co Ltd Formation of contacting hole of semiconductor device

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