JPS6243146A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS6243146A
JPS6243146A JP18330285A JP18330285A JPS6243146A JP S6243146 A JPS6243146 A JP S6243146A JP 18330285 A JP18330285 A JP 18330285A JP 18330285 A JP18330285 A JP 18330285A JP S6243146 A JPS6243146 A JP S6243146A
Authority
JP
Japan
Prior art keywords
silicon
oxide film
main surface
silicon oxide
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18330285A
Other languages
Japanese (ja)
Inventor
Kanji Mukai
向井 幹二
Takeo Yoshikawa
吉川 武夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18330285A priority Critical patent/JPS6243146A/en
Publication of JPS6243146A publication Critical patent/JPS6243146A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent breakdown of a metal wiring at a step on a main surface, by forming a silicon growing layer on the main surface of a semiconductor substrate having a dielectric isolating structure, then performing thermal oxidation, thereby eliminating the step on the main surface on the isolated silicon oxide film. CONSTITUTION:A silicon growing layer 15 is formed on the main surface of a semiconductor substrate 10 having a dielectric isolating structure. The silicon growing layer 15 is oxidized by a thermal oxidation method, and an oxide film 16 is formed. Then, the silicon oxide film 16 is selectively removed by etching, and a part of a single crystal silicon island 14 is exposed. Thereafter, impurities are diffused in the exposed surface of the single crystal silicon by a selective diffusing method, and impurity diffused region 17 is formed. Then, a metal wiring 18 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は誘電体分離構造の半導体集積回路の製造方法に
関し、特に高耐圧が要求される半導体集積回路の製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit having a dielectric isolation structure, and particularly to a method for manufacturing a semiconductor integrated circuit that requires a high breakdown voltage.

〔従来の技術) 従来、この種の半導体集積回路は第2図(71)〜(d
)の工程により製作されていた。すなわち、第2図(a
>に示V誘電体分離構造の半導体基板20を用いて第2
図(+))に示すように、主表面を酸化し、シリコン酸
化膜25を形成する。このシリコン酸化膜25は高耐圧
を実現するためには十分な厚さを必要とする0次に第2
図(C)に示すように、シリコン酸化膜の一部をエツチ
ングし、単結晶シリコン島24の表面を露出させる。次
に第2図(d)に示すように、この単結晶シリコンの露
出面にA択拡散法により不純物を拡散して不純物拡散領
域26を形成し、回路素子を形成し、回路素子間に金属
配線27を施こす。
[Prior art] Conventionally, this type of semiconductor integrated circuit is
) was manufactured using the process. That is, Fig. 2 (a
>A second semiconductor substrate 20 having a V dielectric isolation structure shown in FIG.
As shown in the figure (+), the main surface is oxidized to form a silicon oxide film 25. This silicon oxide film 25 has a zero-order second
As shown in Figure (C), a portion of the silicon oxide film is etched to expose the surface of the single crystal silicon island 24. Next, as shown in FIG. 2(d), impurities are diffused into the exposed surface of this single crystal silicon by the A-type diffusion method to form impurity diffusion regions 26, circuit elements are formed, and metal is placed between the circuit elements. Apply wiring 27.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来・の半導体集積回路の製造方法は、第2図
(b)に示すように、熱酸化によって表面にシリコン酸
化膜25を形成する際、分離シリコン酸化膜22の上に
成長するシリコン酸化膜25は池の部分に比べて非常に
薄くなるために、表面シリコン酸化膜にくぼみ28が生
じる。したがってこの部9)でカ属配線の段切れが生じ
やすいという欠点があった。
In the conventional semiconductor integrated circuit manufacturing method described above, as shown in FIG. Since the film 25 is much thinner than the pond portion, depressions 28 are formed in the surface silicon oxide film. Therefore, there was a drawback that the metal wiring was easily broken in this part 9).

本発明は、上記した従来の方法による欠点を除去し、分
離シリコ/酸化膜上の主表面の段差をなくし、この箇所
における金属配線の段切れを防ぐことが出来る誘電体分
離構造を有する半導体装置の製造方法を提供することを
目的とする。
The present invention eliminates the drawbacks of the conventional methods described above, eliminates the level difference on the main surface of the isolation silicon/oxide film, and provides a semiconductor device having a dielectric isolation structure that can prevent the metal wiring from breaking at this location. The purpose is to provide a manufacturing method for.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体集積回路の製造方法は、複数個の単結晶
シリコン島が第1のシリコン酸化膜を介して多結晶シリ
コン中に埋込まれ、該慎結晶シリコン島の一面を露出し
ている半導体基板の主表面にシリコン成長層を形成する
工程と、該シリコン成長層を熱酸化法により第2のシリ
コン酸化膜に変化させる工程と、該第2のシリコン酸化
膜をエラ千ングにより選択除去し前記慎結晶シリコン島
の一面を露出させる工程と、前記゛ド導体基板の主表面
側から選択拡散法により不純物を前記単結晶シリコン島
内に拡散して回路素子を形成する工程とをきんで構成さ
れる。
A semiconductor integrated circuit manufacturing method of the present invention includes a semiconductor device in which a plurality of single crystal silicon islands are embedded in polycrystalline silicon via a first silicon oxide film, and one surface of the single crystal silicon islands is exposed. A step of forming a silicon growth layer on the main surface of the substrate, a step of changing the silicon growth layer into a second silicon oxide film by a thermal oxidation method, and a step of selectively removing the second silicon oxide film by means of an etching process. The method is comprised of a step of exposing one surface of the single crystal silicon island, and a step of diffusing impurities into the single crystal silicon island from the main surface side of the double-conductor substrate by a selective diffusion method to form a circuit element. Ru.

〔実施例、1 次に、本発明について図面3参照して説明する。[Example, 1 Next, the present invention will be explained with reference to FIG. 3.

第1図(a)〜(d)は本発明の一実施例を説明するた
めに工程順に示した断面図である。
FIGS. 1(a) to 1(d) are cross-sectional views shown in the order of steps for explaining an embodiment of the present invention.

まず、第1図(a)に示すように誘電体分離構造の半導
体基板10の主表面にシリコン成長層15を形成する。
First, as shown in FIG. 1(a), a silicon growth layer 15 is formed on the main surface of a semiconductor substrate 10 having a dielectric isolation structure.

なお図中11は単結晶シリコン島14を支持する多結晶
シリコン、12は分離シリコン酸化膜、13は高濃度埋
込層である。
In the figure, 11 is polycrystalline silicon supporting the single crystal silicon island 14, 12 is an isolation silicon oxide film, and 13 is a high concentration buried layer.

次に、第1図(b)に示すように、熱酸化法によりシリ
コン成長N15を酸化してシリコン酸化膜16を形成す
る。
Next, as shown in FIG. 1(b), the silicon growth N15 is oxidized by a thermal oxidation method to form a silicon oxide film 16.

次に、第1図(c)に示すように、シリコン酸化膜16
を工・ソチングにより選択除去し、単結晶シリコン島1
4の一部を露出させる。
Next, as shown in FIG. 1(c), the silicon oxide film 16
is selectively removed by machining and soching to form single crystal silicon island 1.
Expose part of 4.

次に、第1図((1)に示すように、この単結晶シリコ
ンの露出面に選択拡散法により不純物を拡散し、不純物
拡散領域17を形成し、次いで金属配線18を施すこと
により本実施例による誘電体分離構造の半導体集積回路
が完成する。
Next, as shown in FIG. 1 ((1)), impurities are diffused into the exposed surface of this single crystal silicon by a selective diffusion method to form an impurity diffusion region 17, and then a metal wiring 18 is formed. A semiconductor integrated circuit having a dielectric isolation structure according to the example is completed.

(発明の効果) 以上説明したように本発明は、誘電体分離構造の半導体
基板の主表面にシリコン成長層を形成してから、fil
fi化を行なうことにより分離シリコン酸化膜上の主表
面の段差をなくし、この箇所における金属配線の段切れ
を防ぐ効果がある。
(Effects of the Invention) As explained above, the present invention is capable of forming a silicon growth layer on the main surface of a semiconductor substrate having a dielectric isolation structure, and then forming a film.
The fi formation eliminates the level difference on the main surface of the isolation silicon oxide film and has the effect of preventing the metal wiring from breaking at this location.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)は本発明の一実施例を説明するた
めに工程順に示した断面図、第2図(a)〜(d)は従
来の誘電体分i!if構造の半導体集積回路の製造方法
の一例を説明するために工程順に示した断面図である。 10.20・・・誘電体分離構造の半導体基板、11.
21・・・多結晶シリコン、12.22・・・分離シリ
コン酸化膜、13.23・・・高濃度埋込層、14゜2
4・・・単結晶シリコン島、15・・・シリコン成長層
、16.25・・・シリコン酸化膜、17.26・・・
不純物拡散領域、18.27・・・金属配線、28・・
・シリコン酸化膜のくぼみ。 代理人 弁理士  内 原   昔α 〈 8 l 図 第 2 口
FIGS. 1(a) to 1(d) are cross-sectional views shown in order of steps to explain an embodiment of the present invention, and FIGS. 2(a) to 2(d) are sectional views of a conventional dielectric material i! FIG. 3 is a cross-sectional view shown in order of steps to explain an example of a method for manufacturing a semiconductor integrated circuit having an if structure. 10.20... Semiconductor substrate with dielectric isolation structure, 11.
21... Polycrystalline silicon, 12.22... Isolated silicon oxide film, 13.23... High concentration buried layer, 14゜2
4... Single crystal silicon island, 15... Silicon growth layer, 16.25... Silicon oxide film, 17.26...
Impurity diffusion region, 18.27... Metal wiring, 28...
- Hollow silicon oxide film. Agent Patent Attorney Uchihara Mukashi α 〈 8 l Diagram No. 2

Claims (1)

【特許請求の範囲】[Claims] 複数個の単結晶シリコン島が第1のシリコン酸化膜を介
して多結晶シリコン中に埋込まれ、該単結晶シリコン島
の一面が露出している半導体基板の主表面にシリコン成
長層を形成する工程と、該シリコン成長層を熱酸化法に
より第2のシリコン酸化膜に変化させる工程と、該第2
のシリコン酸化膜をエッチングにより選択除去し前記単
結晶シリコン島の一面を露出させる工程と、前記半導体
基板の主表面側から選択拡散法により不純物を前記単結
晶シリコン島内に拡散して回路素子を形成する工程とを
含むことを特徴とする半導体集積回路の製造方法。
A plurality of single-crystal silicon islands are embedded in polycrystalline silicon via a first silicon oxide film, and a silicon growth layer is formed on the main surface of the semiconductor substrate where one surface of the single-crystal silicon islands is exposed. a step of changing the silicon growth layer into a second silicon oxide film by a thermal oxidation method;
selectively removing the silicon oxide film by etching to expose one side of the single crystal silicon island, and diffusing impurities into the single crystal silicon island from the main surface side of the semiconductor substrate by a selective diffusion method to form a circuit element. A method for manufacturing a semiconductor integrated circuit, comprising the steps of:
JP18330285A 1985-08-20 1985-08-20 Manufacture of semiconductor integrated circuit Pending JPS6243146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18330285A JPS6243146A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18330285A JPS6243146A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6243146A true JPS6243146A (en) 1987-02-25

Family

ID=16133294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18330285A Pending JPS6243146A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6243146A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994025985A1 (en) * 1993-04-28 1994-11-10 Harris Corporation Method and semiconductor device with increased maximum terminal voltage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994025985A1 (en) * 1993-04-28 1994-11-10 Harris Corporation Method and semiconductor device with increased maximum terminal voltage

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