JPS6362145B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generation circuit used for extracting each information bit of information sent by packet transmission, and in particular to a clock pulse generation circuit that is automatically phase-aligned with each information bit of packet transmission information. The present invention relates to a clock pulse generation circuit that generates clock pulses.

Packet transmission improves transmission accuracy and transmission efficiency by transmitting various types of information in blocks, and is used, for example, to transmit character signals in character information transmission television systems. In this case, the text information transmission television system multiplexes text signals (including graphics) onto multiple lines during the vertical retrace period of the television signal and transmits the packets. Character signals sent through transmission are sequentially written into a memory, and the memory information is read out and displayed on the television screen at a cycle synchronized with the horizontal and vertical scanning cycles of the television. Therefore, in a color television signal on which character information is multiplexed, for example, as shown in one horizontal scanning period in FIG. 1, a 296-bit character signal is sent following a horizontal synchronizing signal HS and a color burst signal CB. It is structured as it should be. And this character signal
The CS consists of a running reference signal RI and information data ID.The running reference signal RI is composed of a 2.86MHz 16-bit pulse as shown in an enlarged diagram in Fig. 2, and the information data ID is a running reference signal RI. 5.73MHz synchronized to the pulse period in RI
Non-return-to-zero method (NRZ) with a bit rate of
The signal is represented by

Therefore, when receiving a character signal CS configured as described above, a clock pulse generation circuit is provided inside the character information receiver to generate a clock pulse whose phase and rate match each bit of the received character signal CS. Each information bit of the information data ID is extracted by sampling the CS of the character reception signal using a clock pulse. In this case, the clock pulse generation circuit performs pull-in oscillation by inputting the 2.86MHz run-in reference signal RI extracted separately from the received character signal CS, thereby creating an oscillation circuit that maintains oscillation for approximately one horizontal scanning period. It is used,
The phase and rate of the clock pulses thus generated are matched to each bit of the received character signal CS.

However, the clock pulse generation circuit with the above configuration uses an oscillation circuit that continues to oscillate by being drawn in by the running reference signal RI sent only at the beginning of the character signal CS. The period and phase of the generated clock pulse are determined by the temporary running reference signal RI.
It will be uniquely determined by. As a result, if the phase of the character signal CS changes for some reason, the phase of the sampling clock pulse for each bit of the character signal CS will shift, making it impossible to perform accurate signal processing.

Therefore, an object of the present invention is to provide a clock pulse generation circuit that can always obtain phase-synchronized clock pulses even if the phase of the information bits of the information signal sent by packet transmission varies for some reason. It is.

In order to achieve this object, the clock pulse generation circuit according to the present invention is configured to automatically adjust the phase of the clock pulse generated in accordance with the phase of each information bit of the information signal sent by bucket transmission. It is something. Hereinafter, a clock pulse generation circuit according to the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the clock pulse generation circuit according to the present invention, and particularly shows the case where the clock pulse generation circuit is applied to a text information transmission television receiver. In the figure, 1 inputs a character signal CS as an information signal sent by packet transmission, and this character signal
This is an edge detection circuit that detects the edges of each bit signal of CS, that is, the leading edge and the trailing edge, and generates a sampling pulse SP with a constant pulse width. A differentiating circuit 4, a second differentiating circuit 8 consisting of a capacitor 6 and a resistor 7 for differentiating the character signal CS inverted by the inverter 5, and outputs of the first and second differentiating circuits 4 and 8 as inputs, respectively. The OR gate 9 is configured by an OR gate 9. Reference numeral 10 denotes a D-type flip-flop circuit constituting a phase discrimination circuit, which uses the sampling pulse SP generated from the edge detection circuit 1 as a clock input CK, and also receives a clock pulse CP output from a shift register 16, which will be described later. It is set as D.
If the clock pulse CP lags behind the leading edge of the sampling pulse SP, the output Q is set to "H".
Conversely, for advance, an output is generated. Reference numeral 11 is a 5-bit up/down counter which uses the sampling pulse SP generated from the edge detection circuit 1 as the clock input CK, and uses the output Q of the flip-flop circuit 10 as the control input UP for the up mode, and also controls the output down. The mode control input is DU. Also, this up-down counter 11 has its preset input PR.
A horizontal synchronizing signal HS is input as a signal transmission start signal in packet transmission which is separated from a television signal and is preset to a predetermined value each time this horizontal synchronizing signal HS is supplied. Here, almost 1/2 of the full count value "32"
is set to ``15''. Reference numeral 12 denotes a shift clock generation circuit that generates a shift clock SC corresponding to the count outputs Q _a to Q _e of the up-down counter 11, and a digital clock generator that converts the outputs Q _a to _{Q e} of the up-down counter 11 into corresponding analog values. It is composed of an analog conversion circuit and a voltage-controlled variable frequency oscillator 14 that generates a shift pulse SC of a frequency corresponding to the output of the digital-to-analog conversion circuit 13. 15 corresponds to the basic bit rate of the character signal CS as an information signal sent by packet transmission.
A clock oscillator 16 that generates the original clock pulse CP' of 5.73 MHz receives the original clock pulse CP' as an input, uses the shift clock SC supplied from the shift clock generation circuit 12 as a clock input, sequentially shifts the original clock pulse CP', and then outputs the clock pulse CP' at the output terminal.
This is a shift register that generates a clock pulse CP from OUT, and the phase of the clock pulse CP sent out in response to the shift clock SC supplied from the shift clock generation circuit 12 is varied.

In the clock pulse generation circuit configured in this manner, the clock oscillator 15 continues to generate the original clock pulse CP' of 5.73MHz, which corresponds to the basic bit period of the character signal CS as information sent by packet transmission. , this original clock pulse CP' is supplied to the input terminal IN of the shift register 16.

On the other hand, the up-down counter 11 is set to the central preset value "15" with respect to a predetermined full count value every time the horizontal synchronizing signal HS extracted by separating the television signal is supplied, and the up-down counter 11 is set to the central preset value "15" with respect to the predetermined full count value. In the situation where is not supplied,
This up-down counter 11 outputs a preset output of "15". The digital-to-analog conversion circuit 13 converts the preset value "15" outputted from the up-down counter 11 into a corresponding analog value, and supplies the analog value to the voltage-controlled variable frequency oscillator 14. The voltage controlled variable frequency oscillator 14 generates a shift clock SC having a frequency corresponding to the voltage value supplied from the digital-to-analog conversion circuit 13. Therefore, by sequentially shifting the original clock pulse CP' in accordance with the frequency of the shift pulse SC, the shift register 16 is set so that the phase of the original clock pulse CP' is delayed by approximately half a period and then output as the clock pulse CP. has been done.

Next, when the edge detection circuit 1 is supplied with the character signal CS shown in FIG. A capacitor 6 and a resistor 7 constituting a second differentiating circuit 8 differentiate the inverted signal of the character signal CS supplied via the inverter 5. The thus differentiated output signals of the first and second differentiating circuits 4 and 8 are taken out via the OR gate 9, so that only the positive polarity output is output from each of the character signals CS as shown in FIG. 4b. It will be sent out as a sampling signal SP with a constant pulse width synchronized with the edge portion of the bit.

The sampling pulse generated in this way
The phase relationship between SP and the clock pulse CP generated from the shift register 16 is determined in a flip-flop circuit 10 constituting a phase determining circuit. In other words, the clock pulse CP is the most suitable for sampling each bit signal of the character signal CS.
The phase of is when its leading edge is located at the center of each bit constituting the character signal CS, as shown in FIG. 4c. In this case, since the clock pulse CP is set to 1/2 of the basic bit period of the character signal CS, if the leading edge of the clock pulse CP is located at the center of each bit of the character signal CS, the sampling pulse Phase synchronization is achieved with the leading edge of SP coinciding with the trailing edge of clock pulse CP.
Therefore, the sampling pulse SP is clocked in.
A D-type flip-flop circuit 10 with CK as input and clock pulse CP as input D becomes unstable and outputs Q when the trailing edge of clock pulse CP matches the leading edge of sampling pulse SP. , becomes "H".
For example, when the output Q becomes "H", the up-down counter 11 is set to the down mode, counts the sampling pulse SP, and the count value decreases from the preset value "15" to "14". As a result, the digital-to-analog conversion circuit 13
The signal sent from up-down counter 1
A lowered signal corresponding to the lowering of the count by 1 will be sent out.

In this way, when the output value of the digital-to-analog conversion circuit 13 decreases, the frequency of the shift clock SC output from the voltage-controlled variable frequency oscillator 14 is accordingly decreased.
When the frequency of the shift clock SC is lowered, the shift time of the original clock pulse CP' supplied to the input terminal IN of the shift register 16 to the final stage becomes longer, and the phase of the clock pulse CP generated accordingly changes from that of the previous clock pulse. The clock pulse CP is delayed by one countdown of the up-down counter 11. When the next sampling pulse SP is supplied, the flip-flop circuit 10 determines its phase relationship with the clock pulse CP. In this case, the clock pulse
Since CP is delayed a little, the sampling pulse is generated during the “H” period of clock pulse CP.
SP is generated, and along with this, the output Q becomes "H" and the up-down counter 11
is set to up mode. Therefore, the up-down counter 11 is incremented by the sampling pulse SP and becomes "15" again.
In this way, when the leading edge of the sampling pulse SP and the trailing edge of the clock pulse SP match in phase, the up-down counter 11 alternately performs one-count up and down operations, and accordingly. As a result, the phase of the clock pulse CP will vary slightly. However, since the variation in this case is extremely small, it does not pose any problem, and the sampling pulse SP, that is, the clock pulse CP whose phase is aligned with the character signal CS as an external input signal is obtained.

Next, if the phase of the character signal CS advances for some reason and the phase of the clock pulse CP is significantly delayed as shown in FIG. 4d, the output Q of the D-type flip-flop circuit 10 becomes "H". , the up-down counter 11 is set to the up mode. As a result, the up-down counter 11 is sequentially incremented every time the sampling pulse CP is generated, and each time the count value increases by one count, the cycle of the shift clock SC generated from the shift clock generation circuit 12 increases by one count. As a result, the shift time to the highest output end of the shift register 16 is shortened, and the phase of the generated clock pulse CP is advanced. By performing such an operation every time the sampling pulse SP is generated, the phase of the clock pulse CP is sequentially advanced to match the sampling pulse SP as shown in FIG. 4c. After the leading edge of the sampling pulse SP and the trailing edge of the clock pulse CP coincide,
As described above, the up-down counter 11 repeats the up-down operation every time the sampling pulse SP is input, whereby the phase of the clock pulse CP is automatically adjusted to the sampling pulse SP.

Next, if the phase of the character signal CS is delayed for some reason and the phase of the clock pulse CP greatly advances as shown in Figure 4e, then the sampling pulse
When SP occurs, the output of flip-flop 10 becomes "H" and up-down counter 11 is set to down mode. As a result, each time the sampling pulse CP occurs, the up-down counter increases by 1.
1 is sequentially downcounted, and each time the count value decreases by one, the period of the shift clock SC generated from the shift clock generation circuit 12 is extended, and the phase of the clock pulse CP generated from the shift register 16 is delayed. automatically phased.

This operation is repeated in sequence while the up-down counter 11 is preset again every time the horizontal synchronizing signal HS is generated. An automatically phased clock pulse CP is obtained.

Note that the shift clock generation circuit 12 generates a clock pulse output from the shift register 16 according to the maximum count value of the up-down counter 11.
It is configured so that the phase of CP can be varied over approximately one cycle.

As explained above, the clock pulse generation circuit according to the present invention extracts the original clock pulse output from the clock oscillator as a clock pulse via the shift register, and also outputs the position of the clock pulse for each information bit of information sent by packet transmission. The phase of the clock pulse is varied by varying the cycle of the shift pulse to the shift register in accordance with the phase difference, and along with this, the phase of the clock pulse is always adjusted to each bit of information sent by packet transmission. It has an excellent effect of matching.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing a television signal in which packet-transmitted character signals are multiplexed, Fig. 2 is an enlarged waveform diagram of the character signal shown in Fig. 1, and Fig. 3 is a circuit diagram of a clock pulse generation circuit according to the present invention. Figure, Figure 4a
-e are operation waveform diagrams of each part in FIG. 3. DESCRIPTION OF SYMBOLS 1... Edge detection circuit, 10... Flip-flop circuit, 11... Up-down counter, 12... Shift clock generation circuit, 13... Digital-to-analog conversion circuit, 14... Voltage controlled variable frequency oscillation circuit,
15...Clock oscillator, 16...Shift register.

Claims (1)

[Claims] 1. In a clock pulse generation circuit that generates clock pulses used for extracting each information bit of an information signal sent with a transmission start signal indicating the start of packet transmission, the basics of each information bit of the information signal are A clock oscillator that generates an original clock pulse with a period that matches the bit rate; a shift register that takes in the original clock pulse generated from this clock oscillator as a data input and sequentially shifts it to generate a delayed clock pulse; and each information of the information signal. an edge detection circuit that detects the edge portion of a bit and generates a sampling pulse; a transmission discrimination circuit that detects the delay and advance of the delayed clock pulse with respect to the sampling pulse and generates up and down control signals; an up-down counter which is preset to a predetermined value by a controller and set to up and down modes in response to up and down control signals output from the transmission discrimination circuit, and counts the sampling pulses; A digital-to-analog conversion circuit converts the count output represented by the digital value output from the up-down counter into a corresponding analog signal, and an oscillation output with a frequency corresponding to the output signal level of this digital-to-analog conversion circuit is generated. and a voltage-controlled variable frequency oscillation circuit that supplies the shift register as a shift clock, and always aligns the phase of the delayed clock pulse generated from the shift register with each information bit of information sent by the packet transmission. Clock pulse generation circuit.