JPS6365255B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generation circuit used to extract each information bit of information sent by packet transmission, and in particular to a clock pulse generation circuit that automatically adjusts the phase of each information bit of packet transmission information. The present invention relates to a clock pulse generation circuit that generates synchronized clock pulses.

Packet transmission improves transmission accuracy and transmission efficiency by transmitting various types of information in blocks. For example, in character information transmission television systems, it is used to transmit character signals (including graphics). . In this case, the text information transmission television system multiplexes text signals onto multiple lines during the vertical retrace period of the television signal and performs packet transmission, and on the receiving side, the text is sent by packet transmission. In this system, the character signals that are received are sequentially written into a memory, and the contents of this memory are read out in synchronization with the horizontal and vertical deflection cycles to be displayed on a television receiver. and,
This text information is, for example, multiplexed on the 20th and 22nd lines, and the color television signal on which this text information is multiplexed is structured as shown in FIG. 1, for example. In other words, following the horizontal synchronization signal HS and color burst signal CB, for example, a 296-bit character signal
It is specified that CS will be sent. This character signal CS consists of a running reference signal RI and information data ID, and the running reference signal RI is composed of a 2.86MHz 16-bit pulse, as shown in an enlarged diagram in Fig. 2, and contains information data.
ID is a signal expressed by the non-return-to-zero method (NRZ) with a bit rate of 5.73 MHz synchronized with the pulse period of the running reference signal RI.

Therefore, when receiving a character signal CS configured as described above, a clock pulse generation circuit is provided inside the character information receiver to generate a clock pulse whose phase and rate match each bit of the received character signal CS. Each information bit of the information data ID is extracted by sampling the received character signal CS using a clock pulse. In this case, the clock pulse generation circuit is an oscillation circuit that maintains oscillation for approximately one horizontal scanning period by using the 2.86 MHz running reference signal RI extracted from the received character signal CS as an input signal and performing pull-in oscillation. is used to match the phase and rate of the clock pulses generated thereby to each bit of the received character signal CS.

However, the clock pulse generation circuit with the above configuration uses an oscillation circuit that continues to oscillate by being drawn in by the running reference signal RI sent only at the beginning of the character signal CS. The problem is that the generated clock pulses become unstable over time.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a clock pulse generation circuit that stably and accurately generates clock pulses synchronized with a running reference signal located at the beginning of a packet-transmitted signal. Another object of the present invention is to provide a clock pulse generation circuit that allows easy adjustment of the base oscillation frequency generated from a voltage controlled oscillator. Hereinafter, a clock pulse generation circuit according to the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of a clock pulse generation circuit according to the present invention. In the same figure, 1
is an amplifier circuit that amplifies the television signal A supplied from a tuner (not shown) and supplies it to the character signal sampling circuit 2 and the synchronous separation circuit 3. This synchronization separation circuit 3 receives a vertical synchronization signal included in the television signal supplied from the amplifier circuit 1.
The VS and horizontal synchronizing signal HS are extracted using a generally known method and supplied to the character signal sampling control circuit 4. Character signal extraction control circuit 4 is synchronization separation circuit 3
By counting the horizontal synchronizing signal HS with reference to the vertical synchronizing signal VS supplied from supply Therefore, the character signal sampling circuit 2
is a character signal by extracting the output signal of the amplifier circuit 1 only during the generation period of the sampling control signal B.
CS is taken out. Reference numeral 5 denotes an AND gate which receives the horizontal synchronization signal HS and sampling control signal B, and reference numeral 6 designates a first mono-multivibrator circuit that is triggered by the output of the AND gate 5. A time constant is determined so as to generate an output signal C having a time width including up to the end of the run-in reference signal RI included in the signal CS. Reference numeral 7 denotes an AND gate which receives the output signal C and the character signal CS, and extracts the running reference signal RI in the character signal CS.
Reference numeral 8 denotes a second mono multivibrator circuit that is triggered only once by the first rise of the running reference signal RI generated from the AND gate 7, and the period from the trigger time to the end of generation of the running reference signal RI. A time constant is determined so as to generate a hold control signal D to be supplied to a sample and hold circuit, which will be described later. Therefore, these AND gates 5 and 7 and the first and second monomultivibrator circuits 6 and 8 constitute a sample and hold control circuit 9 that generates a hold control signal D. Reference numeral 10 receives the character signal CS generated from the character signal sampling circuit 2 as input, detects edges in each bit signal of this character signal CS, that is, the leading edge and the trailing edge, and generates a narrow sampling pulse SP. The edge detection circuit consists of a first differentiating circuit 13 consisting of a capacitor 11 and a resistor 12 for differentiating the character signal CS, and a capacitor 15 and a resistor 16 for differentiating the character signal CS inverted by the inverter 14. It is composed of a second differentiating circuit 17 and an OR gate 18 which receives the outputs of the first and second differentiating circuits 13 and 17, respectively. Reference numeral 19 denotes a D-type flip-flop circuit constituting a phase discrimination circuit, which uses the sampling signal SP as a clock input CK and also has a clock pulse CP generated from a voltage controlled oscillator 23 (described later) as a D input. clock pulse CP
A phase discrimination output is generated in which the output Q is set to "H" for a delay, and the output is set to "H" for a lead. 20 is a 4-bit up-down counter which uses the sampling pulse SP generated from the edge detection circuit 10 as a clock input CK;
The output Q of the flip-flop circuit 19 is used as the control input UP for the up mode, and the output is used as the control input DU for the down mode. This up-down counter 20 receives at its preset input PR the horizontal synchronizing signal HS, which is generated from the synchronization separation circuit 3 and serves as a transmission start signal in packet transmission.
It is preset to a predetermined value each time the count value is supplied, and here it is set to "8" which is approximately 1/2 of the full count value "15". 21 is a digital-to-analog conversion circuit that converts the binary count value generated from the output terminals Q _A to Q _D of the up-down counter 20 into an analog value; 22 is a circuit for receiving the output signal E of the digital-to-analog conversion circuit 21; This is a sample and hold circuit that outputs the input signal as it is as an output signal F during the generation period of the sample and hold control signal D supplied from the sample and hold control circuit 9, and the trailing edge of the sample and hold control signal D. The input signal is held and continues to be output. Then, the output signal F of this sample hold circuit 22 is transmitted to the voltage controlled oscillator 23.
is supplied as an oscillation frequency control signal to the flip-flop circuit 19, up-down counter 20, digital-to-analog conversion circuit 21,
The sample hold circuit 22 and the voltage controlled oscillation circuit 23 constitute a phase lock loop.

In the clock pulse generation circuit configured in this way, when a television signal A is supplied from a tuner circuit (not shown), the amplifier circuit 1 amplifies the television signal A and sends it to the character signal sampling circuit 2 and the sync separation circuit. Supply to 3. Then, the synchronization separation circuit 3 separates the vertical synchronization signal VS and horizontal synchronization signal HS contained in the television signal and sends them out. On the other hand, the character signal extraction control circuit 4 counts the horizontal synchronization signals HS based on the vertical synchronization signal VS supplied from the synchronization separation circuit 3, so that the character signal CS is multiplexed into the 20th,
22 lines are discriminated, and a sampling control signal B which becomes "H" only during the period of the 20th and 22nd lines is generated and supplied to the character signal sampling circuit 2. Therefore,
The character signal sampling circuit 2 opens the gate only during the generation period of the sampling control signal B to extract the character signal CS shown in FIG. 6a.

On the other hand, the AND gate 5 determines whether the horizontal synchronization signal HS generated from the synchronization separation circuit 3 and the sampling control signal B match, and determines whether the character signal CS shown in FIG. The first mono-multivibrator circuit 6 is triggered by taking out the rising portion of the horizontal synchronizing signal HS located at . Therefore, this first monomultivibrator circuit 6 receives a horizontal synchronizing signal as shown in FIG. 4b.
Generates an output signal C that rises from the trailing edge of HS. As described above, this first mono multivibrator circuit 6 generates a running reference signal RI whose output signal C is included in the character signal CS.
The time constant is determined to be within the range of time points t ₁ to _{t 4} that sufficiently includes the generation period of the information data ID and does not reach the generation period of the information data ID. The output signal C of the first mono-multivibrator circuit 6 created in this way is used as a gate control signal by the AND gate 7.
, the running reference signal RI included in the character signal CS is extracted, and the second multivibrator circuit 8 is triggered only once at the leading edge of the first signal to generate the sample and hold control signal D. Occur. In this case, the generation period of the sample and hold signal D generated from the second mono multivibrator circuit 8 is equal to the running reference signal RI.
It is a period from time t ₂ to _{t 3} within the period of occurrence of .

On the other hand, the up-down counter 20 receives a horizontal synchronizing signal HS separated from the television signal.
is set to a preset value "8" each time the character signal CS is supplied from the synchronization separation circuit 3, and when the character signal CS is not supplied, the preset output value of the up-down counter 20 is set to "8". is supplied to the digital-to-analog conversion circuit 21. Therefore, the digital-to-analog conversion circuit 21 converts the preset output value "8" of the up-down counter 20 into an analog signal, and the output signal E is sent to the sample hold circuit 22.
supply to. However, at this point, since the sample and hold control signal D is not generated, the sample and hold circuit 22 continues to send out the previously sampled and held value as the output signal F. Therefore, by receiving the previous sample and hold value as the oscillation frequency control signal F, the voltage controlled oscillator 23 oscillates at 5.73 MHz, which is approximately twice the frequency of the character signal CS.

Next, when the running reference signal RI of the character signal CS generated from the character signal sampling circuit 2 is supplied to the edge detection circuit 10, the edge detection circuit 10
is the running reference signal RI shown enlarged in Figure 5a.
The first differentiation circuit 13 differentiates the running reference signal RI, and the second differentiation circuit 17 differentiates the run-in reference signal RI supplied via the inverter 14 and outputs the result. The output signals of the first and second differentiating circuits 13 and 17 differentiated in this way are taken out via the OR gate 18, so that only the positive polarity output is output from each of the running reference signals RI as shown in FIG. 5b. It is sent out as a sampling pulse SP with a constant pulse width synchronized with the edge portion of the bit.

The sampling pulse generated in this way
The phase relationship between SP and the clock pulse CP supplied from the voltage controlled oscillator 23 is determined in a flip-flop circuit 19 constituting a phase determining circuit. In this case, since the flip-flop circuit 16 uses the sampling pulse SP as the clock input and the clock pulse CP as the input D, the fifth
As shown in Figure c, the phase of the clock pulse CP is the most suitable phase for sampling each bit signal of the character signal CS, that is, the sampling pulse SP.
If the leading edge of clock pulse CP lags the phase that coincides with the trailing edge of clock pulse CP, then
During the "H" period, the sampling pulse SP is generated and the set output Q becomes "H". Therefore, since the up-down counter 20 is set to the down mode, it is up-counted every time the sampling pulse SP occurs, and the digital-to-analog conversion circuit 21 converts the count value into an analog value.
The output signal E of will also rise. Also, the clock pulse
If CP is ahead of the sampling pulse SP in phase, the sampling pulse SP is generated during the "L" period of the clock pulse CP, the reset output Q becomes "H", and the up-down counter 20 is set to the down mode and is counted down every time the sampling pulse SP is supplied. Therefore, the output signal E of the digital-to-analog conversion circuit 21 that converts the count output of the up-down counter 20 into an analog value is sampled around the output level corresponding to the preset value of the up-down counter 20, as shown in FIG. It changes in accordance with the phase difference between the delay and lead of the clock pulse CP with respect to the pulse SP. Furthermore, by changing the preset value for the up-down counter here, the base oscillation frequency generated from the voltage controlled oscillator 23 can be easily adjusted.

On the other hand, the sample-and-hold control circuit 9 generates the sample-and-hold control signal D during the generation period of the run-in reference signal RI, as shown in FIG. 4c. Therefore, the sample hold control circuit 22
During the generation period of the sample-and-hold control signal D, the hold is released, and the output signal E of the digital-to-analog converter circuit 21, which fluctuates in accordance with the phase difference, is directly used as the oscillation frequency control signal F to the voltage-controlled oscillator 23. supply to. Therefore, during the generation period of the sample and hold control signal D, a phase lock loop is formed and the oscillation of the voltage controlled oscillator 23 is controlled by the output signal E representing the phase difference, as shown in FIG. 5c. The phase of the clock pulse CP generated is the sampling pulse.
It will be gradually integrated into SP. Then, after a sufficient period of time has elapsed for the two phases to match, the sample and hold control signal D is turned off at time _t3 shown in FIG. 4c. Then, the sample-and-hold circuit 22 latches the output signal E of the digital-to-analog converter 21 at the trailing edge of the sample-and-hold control signal D, as shown at time _t3 in FIG. Its hold level V _H
continues to output. Therefore, when the sample hold control signal D is turned off, the phase lock loop is locked, and the voltage controlled oscillation circuit 23 is fixed to the oscillation condition corresponding to the held oscillation frequency control signal F, and the sampling pulse SP, that is, the character Generation of the clock pulse CP in synchronization with the signal CS is continued until the next sample and hold control signal D is supplied. By performing this operation every time a horizontal synchronizing signal is supplied as a transmission start signal indicating the start of packet transmission, a clock pulse CP whose phase is aligned with the running reference signal RI is stably generated. .

In the above embodiment, the sample and hold control signal supplied to the sample and hold circuit is set to 1 by the first rise of the reference signal RI.
Although the case has been described in which the generation is performed by the second mono-multivibrator circuit that is triggered only once, the present invention is not limited to this, and includes the start point of supply of the run-in reference signal RI and the phase lock. It is sufficient that the signal is generated after the loop becomes stable and continues until the end of the run-in reference signal.

As explained above, according to the clock pulse generation circuit according to the present invention, it is possible to stably and highly accurately generate a clock pulse synchronized with the running reference signal located at the beginning of information sent by packet transmission. Furthermore, once a predetermined value is preset by the transmission start signal, by using an up-down counter that receives the sampling pulse as a count input, the preset value for this up-down counter can be simply changed. , it has various excellent effects such as being able to easily adjust the base oscillation frequency generated from the voltage controlled oscillator.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing a television signal in which packet-transmitted character signals are multiplexed, FIG. 2 is an enlarged waveform diagram of the character signal shown in FIG. 1, and FIG. 3 is a diagram of a clock pulse generation circuit according to the present invention. The circuit diagrams illustrating one embodiment, FIGS. 4a to 4d and 5a to 5c, are operational waveform diagrams of each part of the circuit shown in FIG. 3. 1...Amplification circuit, 2...Character signal sampling circuit,
3... Synchronization separation circuit, 4... Character signal sampling control circuit, 5, 7... AND gate, 6, 8... First and second mono multivibrator circuit, 9... Sample hold control circuit, 10... Edge detection circuit, 19...Flip-flop circuit (phase discrimination circuit), 20...Up-down counter, 21...
Digital-to-analog conversion circuit, 22...sample hold circuit, 23...voltage controlled oscillator.

Claims (1)

[Claims] 1. In a clock pulse generation circuit that generates a clock pulse used for extracting each information bit of an information signal having a running reference signal at the beginning that is sent following a transmission start signal indicating the start of packet transmission, an edge detection circuit that detects the edge of each information bit in the output signal and generates a sampling pulse; and an up-down circuit that uses the sampling pulse as a count input when a predetermined value is preset by the transmission start signal. a counter, a voltage controlled oscillator that generates a clock pulse, a phase discrimination circuit that determines the phase lag and lead of the clock pulse with respect to the sampling pulse and controls up/down mode switching for the up/down counter, and the up/down counter. a digital-to-analog conversion circuit that converts the output signal of the input signal into an analog value; and a sample-and-hold control circuit that generates a sample-and-hold control signal during a period including the start of the run-in reference signal and until the end of the run-in reference signal. During the generation period of the sample-and-hold control signal, the output signal of the digital-to-analog conversion circuit is passed through as is, and the input signal is held and outputted at the trailing edge of the sample-and-hold control signal. A clock pulse generation circuit comprising: a sample hold circuit that supplies an output to the voltage controlled oscillator as an oscillation frequency control signal.