JPS6362144B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generation circuit used for extracting each information bit of information sent by packet transmission, and in particular to a clock pulse generation circuit that is automatically phase-aligned with each information bit of packet transmission information. The present invention relates to a clock pulse generation circuit that generates clock pulses.

Packet transmission improves transmission accuracy and transmission efficiency by transmitting various types of information in blocks, and is used, for example, to transmit character signals in character information transmission television systems. In this case, the text information transmission television system multiplexes text signals (including graphics) onto multiple lines during the vertical retrace period of the television signal and transmits the packets. Character signals sent through transmission are sequentially written into a memory as memory information, and the memory information is read out at a cycle synchronized with the horizontal and vertical scanning cycles of the television and displayed on the screen of the television. Therefore, in a color television signal on which character information is multiplexed, for example, as shown in one horizontal scanning period in FIG. 1, a 296-bit character signal is sent following a horizontal synchronizing signal HS and a color burst signal CB. It is structured as it should be. This character signal CS consists of a running reference signal RI and an information data ID, and is a running reference signal RI.
is 2.86MHz, as shown in the enlarged diagram in Figure 2.
It is composed of 16-bit pulses, and the information data ID is a signal expressed by the non-return-to-zero method (NRZ) with a bit rate of 5.73 MHz synchronized with the pulse period of the running reference signal RI.

Therefore, when receiving a character signal CS configured as described above, a clock pulse generation circuit is provided inside the character information receiver to generate a clock pulse whose phase and rate match each bit of the received character signal CS. Each information bit of the information data ID is extracted by sampling the character reception signal CS using a clock pulse.
In this case, the clock pulse generation circuit performs pull-in oscillation by inputting the 2.86MHz run-in reference signal RI extracted separately from the received character signal CS, thereby creating an oscillation circuit that maintains oscillation for approximately one horizontal scanning period. The phase and rate of the clock pulses generated thereby are matched to each bit of the received character signal CS.

However, the clock pulse generation circuit with the above configuration uses an oscillation circuit that continues to oscillate by being drawn in by the running reference signal RI sent only at the beginning of the character signal CS. The period and phase of the generated clock pulse are determined by the temporary running reference signal RI.
It will be uniquely determined by. As a result, if the phase of the character signal CS changes for some reason, the phase of the sampling clock pulse for each bit of the character signal CS will shift, making it impossible to perform accurate signal processing.

Therefore, an object of the present invention is to provide a clock pulse generation circuit that can always obtain phase-synchronized clock pulses even if the phase of the information bits of the information signal sent by packet transmission varies for some reason. It is.

In order to achieve this object, the clock pulse generation circuit according to the present invention is configured to automatically adjust the phase of the clock pulse generated in accordance with the phase of each information bit of the information signal sent by bucket transmission. It is something. Hereinafter, a clock pulse generation circuit according to the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the clock pulse generation circuit according to the present invention, and particularly shows the case where the clock pulse generation circuit is applied to a text information transmission television receiver. In the figure, 1 inputs a character signal CS as an information signal sent by packet transmission, and this character signal
This is an edge detection circuit that detects the edges of each bit signal of CS, that is, the leading edge and the trailing edge, and generates a sampling pulse SP with a constant pulse width. a second differentiating circuit 8 consisting of a capacitor 6 and a resistor 7 for differentiating the character signal CS inverted by the inverter 5;
The OR gate 9 receives the outputs of the differentiating circuits 4 and 8 as inputs, respectively. Reference numeral 10 denotes a D-type flip-flop circuit constituting a phase discrimination circuit, which inputs a clock pulse CP output from a clock pulse selection circuit 15 to be described later.
In addition, the sampling signal SP is used as the clock input CK, and a phase discrimination output is generated in which the output Q is set to "H" when the clock pulse CP lags with respect to the sampling pulse SP, and the output is set to "H" when the clock pulse CP is ahead. do. 11 is a sampling pulse SP generated from the edge detection circuit 1.
This is a 5-bit up-down counter with clock input CK, and flip-flop circuit 10.
The output Q is used as the control input DO for the down mode, and the output is used as the control input UP for the up mode. In addition, this up-down counter 11
inputs the horizontal synchronization signal HS as a transmission start signal in packet transmission separated from the television signal to its preset input PR.
Each time this horizontal synchronizing signal HS is supplied, it is preset to a predetermined value, and here it is set to "15" which is approximately 1/2 of the full count value "32". 12 is the output terminal of up-down counter 11
Input the binary count value output from Q ^A ~ Q ^E a ~
A decoder converts it into a decimal number as e, and 13 is 5.73M, which corresponds to the basic bit rate of the character signal CS as an information signal sent by packet transmission.
A clock oscillator 14 generates an original clock pulse CP' of Hz, and 14 is a delay line constituting a delay circuit having a plurality of delay output terminals.
It has the same output terminals O ₀ to O ₃₂ as the output terminals of 2, and each output terminal O _{0 to O} 32 is outputted while sequentially delaying the original clock pulse CP' supplied from the clock oscillator 13.
It is configured to output sequentially from _O32 . 1
5 selects the output generated from the output end of the delay line 14 corresponding to the output of the decoder 12,
This is a clock pulse selection circuit that sends out a clock pulse CP that is phase-synchronized with each bit of a character signal CS, and is connected to a decoder 12 and a delay line 1.
The AND gates 16 ₁ to 16 32 determine the coincidence of the signals generated from the corresponding output terminals of the four AND gates 16 1 to 16 ₃₂ , and the OR gate 17 receives the outputs of the AND gates 16 ₁ to 16 ₃₂ as inputs.

In the clock pulse generation circuit configured in this way, the clock oscillator 13 continues to generate the original clock pulse CP' of 5.73 MHz, which corresponds to the basic bit period of the character signal CS as information sent by packet transmission. . This original clock pulse CP' is then supplied to the delay line 14, and outputted to each output terminal _O0 to _O32 while being sequentially delayed in units of 6 ns.

On the other hand, the up-down counter 11 is set to a preset value "15", which is approximately in the middle, each time the horizontal synchronizing signal HS obtained by separating the television signal is supplied, and the character signal CS is supplied. In the state in which the up-down counter 11 is not used, the preset output of the up-down counter 11 is decoded by the decoder 12, and the output is sent out from the output terminal _O15 . And the clock oscillator 13
The original clock pulses CP' generated from CP' are sequentially delayed in the delay line 14, and each time an output is generated from the output terminal _O15 , a coincidence output is sent only from the AND gate ₁₆₁₅ . and,
The output of this AND gate ₁₆₁₅ , that is, the original clock pulse CP', is on the delay line 14 for 6 ns.
×15=90ns delayed signal is clock pulse CP
It will be sent as. In other words, the clock pulse selection circuit 15 selects the delayed output of the delay line 14 corresponding to the output of the decoder 12, and accordingly, the clock pulse selection circuit 15 selects the delayed output of the delay line 14 in accordance with the output of the decoder 12.
CP phase adjustment is performed.

Next, when the edge detection circuit 1 is supplied with the character signal CS shown in FIG. A capacitor 6 and a resistor 7 constituting a second differentiating circuit 8 differentiate the inverted signal of the character signal CS supplied via the inverter 5. The thus differentiated output signals of the first and second differentiating circuits 4 and 8 are taken out via the OR gate 9, so that only the positive polarity output is output from each of the character signals CS as shown in FIG. 4b. It will be sent out as a sampling signal SP with a constant pulse width synchronized with the edge portion of the bit. The sampling pulse SP generated in this way is
Flip-flop circuit 1 constituting a phase discrimination circuit
0, the phase relationship with the clock pulse CP output from the clock pulse selection circuit 15 is determined. In other words, the clock pulse CP is the most suitable for sampling each bit signal of the character signal CS.
The phase of is when its leading edge is located at the center of each bit constituting the character signal CS, as shown in FIG. 4c. In this case, since the clock pulse CP is set to 1/2 of the basic bit period of the character signal CS, if the leading edge of the clock pulse CP is located at the center of each bit of the character signal CS, the sampling pulse Phase synchronization is achieved with the leading edge of SP coinciding with the trailing edge of clock pulse CP.
Therefore, the sampling pulse SP is clocked in.
A D-type flip-flop circuit 10 with input clock CK and clock pulse CP as input D becomes unstable when the clock pulse CP is phase synchronized with the character signal CS as described above, and one of the outputs Q becomes " H”. For example, output Q is “H”
In this case, the up-down counter 11 is set to the up mode, counts the sampling pulse SP, and increases the count value from the preset value "15" to "16". As a result, the decoder 12 generates an output from the output terminal _O16 , and accordingly, the AND gate ₁₆₁₆ selects and takes out the output from the output terminal _O16 of the delay line 14, so that the OR gate 17 The clock pulse CP output from the clock pulse CP is delayed by 6 ns, which is one tap delay time of the delay line 14, with respect to the previous clock pulse CP. When the next sampling pulse SP is supplied, the flip-flop circuit 10 outputs the clock pulse
The phase relationship with CP is determined. In this case, the clock pulse CP is delayed by 6ns, so
This time, the sampling pulse SP is generated during the "H" period of the clock pulse CP, and accordingly, the output becomes "H" and the up-down counter 11 is set to the down mode. Therefore, the up-down counter 11 is counted down to "15" again by the sampling pulse SP. In this way, the sampling pulse
When the leading edge of SP and the trailing edge of clock pulse CP are in phase, the up-down counter 11 increases by one count. The down operation is performed alternately, and the phase of the clock pulse CP becomes a signal that fluctuates by one tap delay of the delay line 14 accordingly. However, since the one-tap delay time in this case is extremely short at 6 ns, there is no problem, and the sampling pulse SP, that is, the clock pulse CP is phase-aligned with the character signal CS as an external input signal.

Next, if the phase of the character signal CS advances for some reason and the phase of the clock pulse CP is significantly delayed as shown in FIG. 4d, the output of the D-type flip-flop circuit 10 becomes "H". , the up-down counter 11 is set to down mode. As a result, each time the sampling pulse SP is supplied, the up-down counter 11 is sequentially down-counted, and the count value becomes 1.
Each time the count decreases, the output generation end of the decoder 12 is shifted downward one by one. Therefore, the output selection end of the clock pulse selection circuit 15 for the delay line 14 is also shifted to the lower direction, and accordingly, the phase of the clock pulse CP is advanced by 6 ns every time the sampling pulse SP is generated. By performing such an operation every time the sampling pulse SP is generated, the phase of the clock pulse CP is sequentially advanced to reach the phase shown in Fig. 4c.
It is matched with the sampling pulse SP as shown in . After these two signals match, the up-down counter 11 repeats the up-down operation every time the sampling pulse SP is input, as described above, so that the clock pulse CP becomes the sampling pulse SP. Automatically phased.

Next, if the phase of the character signal CS is delayed for some reason and the phase of the clock pulse CP greatly advances as shown in Figure 4e, then the sampling pulse
When SP occurs, the output Q of the flip-flop circuit 10 becomes "H" and the up-down counter 11 is set to the up mode. As a result, the up-down counter 11 will be counted up sequentially every time the sampling pulse CP is generated.
Every time the count value increases by one count, the decoder 12
The output generation ends of are shifted upward one by one. Therefore, the clock pulse selection circuit 15
The output selection terminal for the delay line 14 is also shifted to the upper side, and accordingly, the phase of the clock pulse CP is delayed by 6 ns every time the sampling pulse SP is generated. By performing such an operation every time the sampling pulse SP is generated, the phase of the clock pulse CP is successively delayed to match the phase of the character signal CS as shown in FIG. 4c.

Each time the horizontal synchronizing signal HS is generated, the up-down counter 11 is preset again and this operation is repeated in sequence, and along with this, the sampling pulse, that is, the character signal CS as an external input signal is automatically This results in a clock pulse CP whose phase is adjusted exactly.
Note that the delay line 14 is connected to the clock oscillator 1.
The original clock pulse CP′ generated from 3 is approximately 1
The delay time is set so that it can be delayed over a range of cycles (approximately 180 ns), and this allows automatic adjustment even when the phase of the clock pulse CP is shifted to the maximum extent. It is being done. Also, the output end of the delay line 14
The number of terminals for O ₀ to _{O 32} is set so that it can be adjusted even if the phase of the clock pulse CP is shifted by one cycle, and when the up-down counter 11 is preset, the output terminal O ₁₅ in the center is selected. and is configured to be set approximately at the center of the phase adjustment range.

In the above embodiment, a case has been described in which a delay line is used as a delay circuit having a plurality of output terminals that generate sequentially delayed outputs, but the present invention is not limited to this. ,
Needless to say, a shift register that sequentially shifts input signals using shift pulses may be used.

As explained above, the clock pulse generation circuit according to the present invention includes an edge detection circuit that detects the edge portion of each information bit of information sent by packet transmission and generates a narrow sampling pulse, and an edge detection circuit that detects the edge portion of each information bit of information sent by packet transmission and generates a narrow sampling pulse. A predetermined value is preset by a transmission start signal sent at the same time, and an up-down counter that counts the output of the edge detection circuit, and an up-down counter that receives the original clock pulse generated from the clock oscillator and sequentially delays it at a plurality of output terminals. A delay circuit that outputs a signal and a clock pulse selection circuit that selects an output signal sent from each output terminal of the delay circuit corresponding to the output of the up-down counter and sends out a clock pulse are provided. By determining the phase of the clock pulse relative to the pulse, and controlling the up-down counter to the down mode in the case of a lagging phase, and controlling the up-down counter to the up mode in the case of the leading phase,
It automatically aligns the generated clock pulses with the information bits of the information sent by packet transmission. Therefore, even if the phase of the information bits of information sent by packet transmission changes for some reason, there is an excellent effect in that automatically phase-aligned clock pulses can always be obtained.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram showing a television signal in which packet-transmitted character signals are multiplexed, Fig. 2 is an enlarged waveform diagram of the character signal shown in Fig. 1, and Fig. 3 is a circuit diagram of a clock pulse generation circuit according to the present invention. , Figure 4 a~
e is a waveform chart showing the operation of each part in FIG. DESCRIPTION OF SYMBOLS 1... Edge detection circuit, 10... Flip-flop circuit, 11... Up-down counter, 12... Decoder, 13... Clock oscillator, 14... Delay line, 15... Clock selection circuit.

Claims (1)

[Claims] 1. In a clock pulse generation circuit that generates a clock pulse used for extracting each information bit of an information signal sent with a transmission start signal indicating the start of packet transmission, the edge of each information bit of the information signal is an edge detection circuit that detects and generates a sampling pulse; an up-down counter that is preset to a predetermined value determined by the transmission start signal and uses the sampling pulse as a count input; and a basic bit rate of the information signal. a delay circuit which inputs an original clock pulse with a period corresponding to , and outputs sequentially delayed delayed clock pulses from a plurality of output terminals, and outputs from each output terminal of the delay circuit according to the count value output from the up-down counter. A clock pulse selection circuit selects and sends out one of the delayed clock pulses, and determines whether the phase of the trailing edge of the clock pulse outputted from this clock pulse selection circuit is ahead or behind the leading edge of the sampling pulse. A phase discrimination circuit is provided to control the up-down counter to a down mode when the clock pulse is in a lagging phase, and to control the up-down counter to an up mode when the clock pulse is in an advanced phase. A clock pulse generating circuit characterized in that the clock pulse generated by the clock pulse is always aligned in phase with each information bit of the information signal sent by the packet transmission.