JPS6254271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generator used for extracting each information bit of information sent by packet transmission. More particularly, the present invention relates to a clock pulse generator for generating clock pulses that are automatically phase aligned with each information bit of packet transmission information.

Packet transmission improves transmission accuracy and transmission efficiency by transmitting various types of information in blocks, and is used, for example, to transmit character signals in the television multiplex broadcasting system. In this case, the television text multiplex broadcasting system multiplexes character signals (including graphics) onto multiple lines during the vertical blanking period of a composite video signal and transmits them as packets. The character signals are sequentially written into the memory, and the memory information is read out at intervals synchronized with the horizontal and vertical scanning of the television receiver and displayed on the screen of the television receiver. Therefore, a color composite video signal on which character information is multiplexed is generated by a horizontal synchronizing signal HS, a color burst signal, and a color burst signal, for example, as shown in FIG.
The configuration is such that, for example, a 296-bit character signal is sent following the CB. This character signal CS consists of a running reference signal RI and information data ID, and the running reference signal RI is composed of a 2.86MHz 16-bit pulse, as shown in an enlarged diagram in Fig. 2, and contains information data. ID was synchronized with the pulse period of the running reference signal RI.
The signal is expressed using the non-return-to-zero method (NRZ) with a bit rate of 5.73MHz.

Therefore, a character signal configured in this way
When receiving CS, a clock pulse generator that generates a clock pulse whose phase and rate match each bit of the character signal CS is provided inside the character information receiver, and this clock pulse is used to sample the character signal CS. Each information bit of the information data ID is extracted.
In this case, the clock pulse generator
An oscillation circuit is used that sustains oscillation for approximately one horizontal scanning period by inputting the 2.86 MHz running reference signal RI extracted separately from the CS and performing pull-in oscillation. The phase and rate of the clock pulses are matched to each bit of the character signal CS.

However, the clock pulse generator with the above configuration uses an oscillation circuit that continues to oscillate by being drawn in by the run-in reference signal RI sent only at the beginning of the character signal CS. The period and phase are uniquely determined by the temporary running reference signal RI. As a result, if the phase of the character signal CS changes for some reason, the phase of the sampling clock pulse for each bit of the character signal CS will shift, making it impossible to perform accurate signal processing.

An object of the present invention is to provide a clock pulse generator that can always obtain phase-synchronized clock pulses even if the phase of the information bits of the information signal sent by packet transmission varies for some reason.

In order to achieve this object, the clock pulse generator according to the present invention is configured to automatically adjust the phase of the clock pulse generated in accordance with the phase of each information bit of the information signal sent by packet transmission. It is something. The present invention will be explained below with reference to the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the clock pulse generator according to the present invention, particularly when applied to a television receiver for teletext broadcasting. In the figure, 1 inputs a character signal CS as an information signal sent by packet transmission, detects the edges of each bit signal of this character signal CS, that is, the leading edge and the trailing edge, and generates a sampling pulse of a constant pulse width. a first differentiating circuit 4 which is a first edge detection circuit that generates SP and is composed of a capacitor 2 and a resistor 3 that differentiates a character signal CS;
A second differentiating circuit 8 consisting of a capacitor 6 and a resistor 6 differentiates the character signal inverted by the inverter 5, and an OR gate 9 receives the outputs of the first and second differentiating circuits 4 and 8 as inputs. It is composed of Reference numeral 10 denotes a D-type flip-flop circuit constituting a phase discrimination circuit, which receives the sampling pulse SP generated from the first edge detection circuit 1.
is the clock input CK, and the second
The clock pulse CP output from the shift register 162 is input D, and when the clock pulse CP lags behind the leading edge of the sampling pulse SP, the output Q becomes "H", and when it leads, the output Q becomes "H". occurs. 11 is, for example, a 5-bit up-down counter which uses the sampling pulse SP generated from the first edge detection circuit 1 as the clock input CK, and uses the output Q of the flip-flop circuit 10 as the up-mode control input UP.
At the same time, the output is used as the down mode control input DU. Further, this up-down counter 11 receives, at its preset input PR, a horizontal synchronizing signal HS as a signal transmission start signal in packet transmission separated from the composite video signal. Therefore, the up-down counter 11 is preset to a predetermined value each time this horizontal synchronizing signal HS is supplied, and here, for example, it is set to "15" which is approximately 1/2 of the full count value "32". be done. 12 is a shift clock generation circuit that generates a first shift clock SC1 and a second shift clock SC2 corresponding to the count outputs _{Q A to Q E of} the up-down counter 11; Digital-to-analog conversion circuit 131 for converting into analog values
(hereinafter referred to as the D/A conversion circuit 131) and the D/A conversion circuit 131.
a first shift clock SC1 that generates a first shift clock SC1 having a first frequency corresponding to the output of the conversion circuit 131;
Voltage controlled variable frequency oscillator 141 (hereinafter referred to as
1VCO 141) and a second shift clock SC having a second frequency higher than the first frequency.
2. A second voltage controlled variable frequency oscillator 1 that generates
42 (hereinafter referred to as the second VCO 142) and a sampling hold circuit 132. The sampling hold circuit 132 is the first VCO
141, the output from the D/A conversion circuit 131 is relayed, and the analog value to be relayed is updated each time a sampling pulse SP is supplied from the hold pulse generation circuit 18, which will be described later. The above-mentioned updating is stopped by supplying the hold pulse HP created in place of the sampling pulse SP from the hold pulse creation circuit 18. Therefore, the
The frequency control voltage applied to the 1VCO 141 is fixed to the analog value of the output of the D/A conversion circuit 131 at the time when the hold pulse HP is supplied to the sampling and holding circuit 132. 1
5 is a clock oscillator that generates an original clock pulse OCP of 5.73 MHz, which matches the basic bit rate of the character signal CS as an information signal sent by packet transmission. 161 is the original clock pulse
Shift clock generation circuit 12 with OCP as input
After sequentially shifting the original clock pulse OCP using the first shift clock SC1 supplied from the output terminal OUT as a drive pulse,
This is the first shift register that supplies the shift register 162. As a result, the first shift register 161 varies the phase of the clock pulse CP sent from the output terminal 20 in response to the first shift clock SC1 supplied from the shift clock generation circuit 12. Similarly, the second shift register 162
Also, in response to the shift clock SC2 supplied from the shift clock generation circuit 12, the phase of the clock pulse CP sent from the output terminal 20 is varied. Therefore, the first and second shift registers 161 and 162 are connected to the first and second VCO 14.
The amount of delay relative to the clock pulse CP is varied in accordance with the frequency changes of the first and second shift clocks SC1 and SC2 provided by the clock pulses 1 and 142, respectively. Here, the second VCO 142 is the first VCO 141
Since it is set in advance to change at a higher frequency than the first shift register 161, the change in the delay amount of the first shift register 161 is a so-called coarse adjustment, and the change in the delay amount of the second shift register 162 is a fine adjustment.

Here, 17 is a phase discrimination circuit, that is, a second edge detection circuit for detecting the leading edge of the output of the flip-flop circuit 10, which includes a capacitor 171 and a resistor 172.
A third differentiating circuit 173 formed by a capacitor 174 and a resistor 175, a fourth differentiating circuit 176 formed by a capacitor 174 and a resistor 175, and an OR gate 178. This third differentiating circuit 173 is connected to the output Q of the flip-flop circuit 10 forming a phase discrimination circuit.
Detects the edge when the signal is reversed to “H”, and
Differentiator circuit 176 detects the edge when the output is inverted to "H". This third and fourth differentiating circuit 1
Both outputs of 73 and 176 are OR gate 1, respectively.
It is supplied to the hold pulse generation circuit 18 via 78. The hold pulse generating circuit 18 is composed of a flip-flop circuit 181 and an AND gate 182. The flip-flop circuit 181 receives the output of the above-mentioned OR gate 178 as a clock input at a terminal CK, and receives the horizontal synchronizing signal HS supplied from a terminal 192 as a clear signal at a terminal CLR. Further, the output controls the opening and closing of the AND gate 182. This and gate 18
2 is constantly supplied with the sampling pulse SP output from the first edge detection circuit 1 already mentioned, and outputs this sampling pulse SP in accordance with the opening and closing of the gate. Furthermore, when the gate is closed and the sampling pulse SP is not output, the output terminal of the AND gate 182 is maintained at "L" as the hold pulse HP.

By the way, each time the up-down counter 11 is supplied with the horizontal synchronizing signal HS obtained by separating the composite video signal, the up-down counter 11 sets the central preset value "15" to the predetermined full count value "32".
When the character signal CS is not supplied, the up-down counter 11 outputs the preset value "15" as described above. The D/A conversion circuit 131 outputs a voltage obtained by converting the preset value "15" output from the up-down counter 11 into a corresponding analog value. At this time, since the above-mentioned hold pulse HP is not given to the sampling hold circuit 132, the output of the D/A conversion circuit 131 is
1. The first VCO 141 generates a first shift clock SC1 having a frequency corresponding to the voltage value supplied from the D/A conversion circuit 131. Therefore, the first shift register 161 sequentially shifts the original clock pulse OCP in accordance with the frequency of the first shift clock SC1. Similarly, the second shift register 162 further shifts the original clock pulses by the second VCO 142. At this time, the first
The shift by the shift clock SC1 is set so that the phase of the original clock pulse OCP is delayed by approximately half a period before being outputted to the second shift register 162.

Next, when the first edge detection circuit 1 is supplied with the character signal CS shown in FIG. A capacitor 6 and a resistor 7 constituting a second differentiating circuit 8 differentiate the character signal supplied via the inverter 5. The thus differentiated output signals of the first and second differentiating circuits 4 and 8 are taken out via the OR gate 9, so that only the positive polarity output is shown in FIG. 4b.
It is pulled out as shown. This is the character signal CS
is extracted as a sampling pulse SP with a constant pulse width synchronized with the edge portion of each bit.

The sampling pulse generated in this way
The phase relationship between SP and the clock pulse CP drawn from the output terminal 20 is determined in the flip-flop circuit 10 constituting the phase determining circuit. In other words, the most suitable phase of the clock pulse CP for sampling each bit signal of the character signal CS is when its leading edge is located in the center of each bit constituting the character signal CS, as shown in Figure 1c. Then, convert this into a flip-flop circuit 10.
Distinguish by.

Here, since the clock pulse CP is set to 1/2 of the basic bit period of the character signal CS, if the leading edge of the clock pulse CP is located at the center of each bit of the character signal CS, the sampling pulse Phase synchronization is achieved with the leading edge of SP matching the trailing edge of clock pulse CP. Therefore,
Sampling pulse SP is used as clock input CK,
A D-type flip-flop circuit 10 which receives a clock pulse CP as an input D has a clock pulse CP as an input D.
When the trailing edge of the sampling pulse SP is phase-synchronized to match the leading edge of the sampling pulse SP, an unstable state occurs and either of the outputs Q and Q becomes "H".

Below, for example, a case where the output becomes "H" will be explained. In this case, the up-down counter 11 is set to the down mode, counts the sampling pulse SP, and the count value decreases from the preset value "15" to "14". the result,
The signal sent out from the D/A conversion circuit 131 is lowered in response to the one count decrease of the up-down counter 11. In this way, when the output value of the D/A conversion circuit 131 decreases, the frequency of the shift clock SC2 output from the second VCO 142 is decreased accordingly. On the other hand, since the hold pulse HP is not applied to the sampling hold circuit 132 in the first VCO 141 as described above, the output value of the D/A conversion circuit 131 is applied as is, similar to the second VCO 142 described above. Therefore, at the same time as the frequency of the first shift clock SC1 is lowered, the frequency of the second shift clock SC2 is also lowered. At this time, the second VCO 142
Since the frequency of the up-down counter 11 is set higher than that of the first VCO 141,
The frequency reduction of the shift clock per count is smaller in the second shift clock SC2 than in the first shift clock SC1. As a result, the phase of the original clock pulse OCP is largely changed by the first shift register 161,
Here, the shift time until the output terminal 20 reaches the final stage becomes longer. Accordingly, the phase of the clock pulse CP generated at the output terminal 20 is delayed by one countdown of the up-down counter 11 with respect to the previous clock pulse CP. Then, when the next sampling pulse SP is supplied, the flip-flop circuit 10 receives the clock pulse.
The phase relationship with CP is determined. In this case, the first
Since the delay amount by the shift register 161 is larger than that by the second shift register 162, the original clock pulse OCP is first generated as a sampling pulse SP during the "H" period of the clock pulse CP due to the delay amount of the first shift register 161. The timing will be delayed. Along with this, the output Q of the flip-flop circuit 10 becomes "H" and the up-down counter 11 is set to the up mode. At the same time, the third differentiating circuit 173 of the second edge detection circuit 17
The inversion of the output Q of 0 is detected and the flip-flop circuit 181 of the hold pulse generation circuit 18 is set. Therefore, the gate of the AND gate 182 is closed, and the supply of the sampling pulse SP that has passed through the AND gate 182 to the sampling and hold circuit 132 is cut off, and at the same time, the "L" hold pulse HP is supplied to the sampling and hold circuit 132. Given. As a result, the control voltage applied to the first VCO 141 is fixed regardless of changes in the count output of the up-down counter 11, and its oscillation frequency is also fixed. On the other hand, the up-down counter 11 is counted up by the sampling pulse SP and becomes "15" again. However, at this time, since the phases of the leading edge of the sampling pulse SP and the trailing edge of the output pulse of the first shift register 161 match, the phase of the original clock pulse OCP is changed by the second shift register 162, and furthermore, the phase of the original clock pulse OCP is changed by the second shift register 162. The phase of clock pulse CP is delayed. Then, the phases of the trailing edge of the clock pulse CP and the leading edge of the sampling pulse SP vary slightly. The phase fluctuation at this time is extremely small and does not pose a practical problem. As a result, the clock pulse CP is extracted from the output terminal 20 in phase with the sampling pulse SP, that is, the character signal CS as an external input signal.

Next, a case will be described in which the phase of the character signal CS advances for some reason and the phase of the clock pulse CP is significantly delayed as shown in FIG. 4d. In this case, the output Q of the D-type flip-flop circuit 10 becomes "H" and the up-down counter 1
1 is set to up mode. As a result, the up-down counter 11 is sequentially incremented every time the sampling pulse SP is generated, and each time the count value increases by one count, the first and second shift clocks SC1 and SC2 generated from the shift clock generation circuit 12 are incremented. The cycle is shortened by one count up. Further, in conjunction with this, the shift time to the highest output end of the first and second shift registers 161, 162 is shortened and generated for each step, and the phase of the clock pulse CP is advanced. At this time, since the shift time by the first shift register 161 is longer than that by the second shift register 162, the up-down counter 1 until the leading edge of the sampling pulse SP is found.
1 count step is the second shift register 16
There are fewer first shift registers 161 than 2. As a result, the first shift register 161 performs a coarse phase adjustment until the original clock pulse OCP finds the leading edge of the sampling pulse. Then, the second
When the edge detection circuit 17 detects this, the second shift register 161 then enters fine adjustment. The first and second shift registers 161 and 162 perform this operation every time the sampling pulse SP is generated, so that the phase of the clock pulse CP is sequentially advanced to match the sampling pulse SP as shown in FIG. 4c. . After the leading edge of the sampling pulse SP and the trailing edge of the clock pulse CP match, the up-down counter 11 alternately repeats the up-down operation every time the sampling pulse SP is input, as described above. This automatically adjusts the phase of the clock pulse CP to the sampling pulse SP.

Next, a case will be described in which the phase of the character signal CS is delayed for some reason and the phase of the clock pulse CP advances significantly as shown in FIG. 4e. In this case, when the sampling pulse SP is generated, the output of the flip-flop circuit 10 becomes "H", and the up-down counter 11 is set to the down mode. As a result, the up-down counter 11 is sequentially down-counted every time the sampling pulse SP is generated, and each time the count value decreases by one count, the first and second shift clocks SC1 and SC2 generated from the shift clock generation circuit 12 are incremented. The period is lengthened and the first and second
The phases of clock pulses CP generated from shift registers 161 and 162 are delayed to automatically perform coarse and fine phase adjustment.

The above operations are sequentially repeated while presetting and clearing the up-down counter 11 and flip-flop circuit 181 each time the horizontal synchronizing signal HS is generated, depending on the phase advance or lag of the character signal CS.

Note that the shift clock generation circuit 12 is configured to be able to vary the phase of the clock pulse CP output from the first and second shift registers 161 and 162 over approximately one cycle according to the maximum count value of the up-down counter 11. ing.

As explained above, the clock pulse generator according to the present invention extracts the original clock pulse output from the clock oscillator as a clock pulse through the first and second shift registers, and outputs each information bit of information sent by packet transmission. Find the phase difference of the above clock pulse with respect to
The period of the shift clock pulse that drives the first and second shift registers is varied in accordance with this phase difference, thereby varying the phase of the clock pulse ultimately extracted from the first and second shift registers. Therefore, the present invention has the excellent effect of always making the phase of the clock pulse coincide with each information bit of information sent by packet transmission.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram showing a composite video signal in which packet-transmitted character signals are multiplexed.
FIG. 3 is a circuit diagram of an embodiment of the clock pulse generator according to the present invention, and FIGS. 4 a to 5 e and 5 a to d are operation waveform diagrams of each part of FIG. be. DESCRIPTION OF SYMBOLS 1...First edge detection circuit, 10...Flip-flop circuit, 11...Up-down counter, 12...
Shift clock generation circuit, 131...Digital-to-analog conversion circuit, 15...Clock oscillator, 132
... Sampling hold circuit, 18... Hold pulse generation circuit, 141... First voltage controlled variable frequency oscillator, 142... Second voltage controlled variable frequency oscillator, 161... First shift register, 162... Second shift register, 17... a second edge detection circuit;
181...Flip-flop circuit, 182...AND gate.

Claims (1)

[Scope of Claims] 1. A clock pulse generator for generating clock pulses used for extracting each information bit of an information signal sent by packet transmission, which detects the edge of each information bit of the information signal. a first edge detection circuit that generates a sampling pulse; an up-down counter that is set to a predetermined value determined in advance by the transmission start signal indicating the start of packet transmission and that uses the sampling pulse as a count input; a clock oscillator that generates an original clock pulse at a frequency that matches the basic bit rate of the information signal; a digital-to-analog conversion circuit that converts the count output of the up-down counter to a predetermined voltage level and outputs the voltage level; a first voltage-controlled variable frequency oscillator whose oscillation frequency is varied according to the voltage level held by the sampling and hold circuit; a first shift register driven by a clock supplied from the first voltage-controlled variable frequency oscillator; and a first shift register driven by a clock supplied from the first voltage-controlled variable frequency oscillator; a second voltage-controlled variable frequency oscillator whose oscillation frequency is variable, which is different from the oscillation frequency of the frequency oscillator; and an output of the first shift register as input;
a second shift register driven by a clock provided by the second voltage controlled variable frequency oscillator; and a second shift register driven by a clock provided by the second voltage controlled variable frequency oscillator; A phase for determining whether the phase of the edge is leading or lagging, and controlling the up-down counter to the up mode if the clock pulse is in the leading phase, and controlling the up-down counter to the down mode if the clock pulse is in the lagging phase. a discriminating circuit; a second edge detecting circuit for detecting a change point of the mode of the phase discriminating circuit; supplying the sampling pulse output from the first edge detection circuit to the sampling hold circuit, and cutting off the supply of the sampling pulse by receiving the output of the second edge detection circuit; and a hold pulse generating circuit that generates and outputs a hold pulse so as to maintain the holding voltage level at this point in time, and the clock pulse outputted from the second shift register is always connected to the information sent by the packet transmission. A clock pulse generator characterized by being phase-aligned with each information bit of a signal.