JPS58116829A - Clock pulse generating circuit - Google Patents
Clock pulse generating circuitInfo
- Publication number
- JPS58116829A JPS58116829A JP56210398A JP21039881A JPS58116829A JP S58116829 A JPS58116829 A JP S58116829A JP 56210398 A JP56210398 A JP 56210398A JP 21039881 A JP21039881 A JP 21039881A JP S58116829 A JPS58116829 A JP S58116829A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- pulses
- generated
- signal
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Abstract
PURPOSE:To obtain invariably phase-locked clock pulses by performing an automatic phase adjustment of clock pulses generated in correspondence to the phase of respective information bits of a transmitted information signal. CONSTITUTION:When supplied with a character signal CS, an edge detecting circuit 1 generates sampling pulses SP synchronizing with edges of respective information bits of the signal CS. Those pulses SP are supplied to an FF10 to decide on phase relation with the clock pulses SP outputted from a shift register 16. If the signal CS leads in phase and the pulses CP lag in phase, the output Q of the FF circuit 10 goes up to a level H and an up/down counter 11 is placed in up mode. Consequently, every time the pulse CP is generated, the counter 11 counts up successively and every time its counted value increases by one, the period of a shift clock SC generated by a shift clock generating circuit 12 is shortened. Consequently, the phase of the pulses CP generated by the register 16 is advanced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56210398A JPS6362145B2 (en) | 1981-12-30 | 1981-12-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56210398A JPS6362145B2 (en) | 1981-12-30 | 1981-12-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58116829A true JPS58116829A (en) | 1983-07-12 |
JPS6362145B2 JPS6362145B2 (en) | 1988-12-01 |
Family
ID=16588656
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56210398A Expired JPS6362145B2 (en) | 1981-12-30 | 1981-12-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6362145B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS497979A (en) * | 1972-05-11 | 1974-01-24 |
-
1981
- 1981-12-30 JP JP56210398A patent/JPS6362145B2/ja not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS497979A (en) * | 1972-05-11 | 1974-01-24 |
Also Published As
Publication number | Publication date |
---|---|
JPS6362145B2 (en) | 1988-12-01 |
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