JPS6362113B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a floating gate structure and a nonvolatile memory function.

Technical background of the invention and its problems In recent years, demand for electrically rewritable nonvolatile semiconductor memories has increased. Conventionally, there are two main types of electrically rewritable nonvolatile semiconductor memory: MNOS (metal nitride, oxide semiconductor) structure type memory and floating gate structure type memory. The former MNOS structure type memory generally has a memory retention characteristic inferior to the latter floating gate structure type memory, and has the property that this memory retention characteristic worsens as the temperature rises. In this respect, floating gate structure memory has come to be considered to be the most suitable electrically rewritable nonvolatile semiconductor memory, and research and development in this direction has become active. A structural sectional view of such a conventional floating gate structure type memory is shown in FIG. In this memory, a floating gate electrode 2 provided on a P-type silicon substrate 1 is
The N ⁺ type diffusion regions 3 and 4 overlap with each other via a silicon oxide film 5 of about 200 Å, and charges are exchanged between the N ⁺ type drain region 4 and the floating gate electrode 2, and data is transferred. Perform erasing and writing. For example, in the case of erasing data, by applying a voltage of approximately +20V to the drain region 4 and setting the control gate voltage applied to the control gate electrode 6 to 0V, a Fuaura-Nordheim shape is applied from the floating gate electrode 2 to the drain region 4. This is done by emitting electrons through the tunnel effect. Conversely, when writing data, the drain region 4 is set to 0V, and the control gate electrode 6 is set to about +
By applying a voltage of 20V, the drain region 4
This is done by injecting electrons into the floating gate electrode 2 using a Fuaura-Nordheim type tunnel effect.

However, the semiconductor memory device described above has the following drawbacks when miniaturized. That is, in order to apply a large voltage of about 20 V to the drain region 4 made of an N ⁺ diffusion region during erasing, when the storage transistor is miniaturized according to the proportional reduction law, the voltage between the drain 4 and the source 3 increases. There were disadvantages in that miniaturization did not proceed as expected due to the punch-through phenomenon in which the depletion layer was connected and the pn junction breakdown between the drain 4 and the silicon substrate 1. The inability to achieve miniaturization through proportional reduction means that the bit density of this semiconductor memory device cannot be increased, and furthermore, the read speed cannot be increased. Furthermore, when constructing a memory cell array using the memory elements shown in FIG. 1, it is necessary to add a selection transistor in series with the drain region 4, and one memory cell is composed of two transistor elements. This has the disadvantage that the area required per memory cell becomes even larger.

OBJECTS OF THE INVENTION The present invention was made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a nonvolatile semiconductor memory device with high bit density and high read speed.

SUMMARY OF THE INVENTION First, to give an overview of the present invention, in the present invention, the semiconductor regions that constitute the source region, active region (region where a channel is formed), and drain region of a floating gate transistor are completely insulating. The conventional drawbacks have been eliminated by introducing a structure in which a conductive layer is provided separated by a distance, and the floating gate electrode of the floating gate transistor is disposed on this conductive layer via an insulating thin film that allows charge exchange. ing. That is, in this structure, the charge amount control terminal region made of a conductive layer that exchanges charge with the floating gate electrode using the Fuaura-Nordheim type tunnel effect as in the past is completely surrounded by an insulator. , the fear of punch-through phenomenon and the pn junction breakdown voltage are irrelevant, so the structure can be significantly miniaturized in accordance with the law of proportional reduction. Therefore, a semiconductor memory device with high bit density and high read speed can be obtained. Furthermore, this floating gate type transistor is suitable for increasing bit density in that an electrically rewritable semiconductor memory device can be configured with basically one transistor per cell, except that it has a charge amount control terminal made of a conductive layer. There is.

Embodiments of the Invention Specific embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows the structure of the semiconductor memory device of the present invention, FIG. 2a is a plan view thereof, and FIGS.
It is a sectional view taken along the line −C′. Figure 2 a, b,
As shown in c, on an insulating substrate 11 made of sapphire, for example, a source region 13, an active region 12,
A first semiconductor region, for example, a first single crystal silicon island region (semiconductor region) 15 having a thickness of 0.5 μm and consisting of a drain region 14 is provided. Further, the first single crystal silicon island 15 is formed on this insulating substrate 11.
and a second semiconductor region completely separated by an insulating material 16, for example a second single crystal silicon island 17.
A charge control terminal region (conductive layer) 18 having a film thickness of 0.5 μm is provided. The active region 12 in the first single crystal silicon island region 15 is, for example, 10 ¹⁶ cm ^-3
This region 12 is a P-type region containing boron impurities, and a P-type or n-type region made of a polycrystalline silicon film 3000 Å thick is formed on this region 12 via a gate insulating film 19 made of a silicon oxide film 500 Å thick. A floating gate electrode layer 20 is provided. Charge amount control terminal region 18 made of the second single crystal silicon island 17
is formed, for example, in a P ⁺ type region containing 10 ¹⁸ cm ^-3 or more of boron impurity. This charge amount control terminal area 18
The upper part overlaps with a part of the floating gate electrode layer 20 through a silicon oxide film 21 with a thickness of 500 Å. The charge amount control terminal region 18 and the floating gate electrode layer 20 are made to face each other with the insulating thin film 22 interposed therebetween. Further, on this floating gate electrode layer 20, a control gate electrode wiring 24 made of a polycrystalline silicon layer with a thickness of 4000 Å is provided via a second gate insulating film 23 made of a silicon oxide film with a thickness of about 800 Å. It is being A field insulating film 25 made of a silicon oxide film is formed on the control gate electrode wiring 24, and a bit line 26 and a charge amount control line 27 made of aluminum metal wiring are provided thereon. This bit line 26 is connected to the drain region 14.
The charge amount control line 27 is connected to the charge amount control terminal region 18 through a contact region 29 . Note that spinel or silicon oxide may be used as the insulating substrate. Note that when silicon oxide is used, the first and second semiconductor regions may be formed on the semiconductor substrate via the silicon oxide.

Next, the operation of the semiconductor memory device configured as described above will be explained. Here, floating gate electrode layer 2
A state in which electrons are injected into the floating gate electrode 20 is defined as an information "1" state, and conversely, a state in which electrons are emitted from the floating gate electrode 20 is defined as an information "0" state.
To write information “1”, first write the charge amount control terminal 2.
7, apply a voltage of 0V to charge amount control terminal area 1.
Set the potential of 8 to 0V. Next, a voltage pulse of +15 V and a pulse width of 1 mS is applied to the control gate electrode wiring 24. As a result, electrons are injected from the electron charge amount control terminal region 18 into the floating gate electrode layer 20 through the thin silicon oxide film 22 of about 150 Å, and information "1" is written.

Conversely, when writing information "0", the potential of the control gate electrode wiring 24 is maintained at 0V, and the charge amount control terminal 27 is supplied with +15V and a pulse width of 1mS.
Apply a voltage pulse of . This results in approximately 150Å
Electrons are emitted from the floating gate electrode layer 20 to the charge amount control terminal region 18 through the thin silicon oxide film 22, and information "0" is written. As a result of the write operation as described above, the control gate electrode 24
is the gate, source region 13, drain region 1
The threshold voltage of the transistor with 4 is information “1”,
When the information is "0", the voltage becomes +6V and +1V, respectively.

FIG. 3 shows, for example, a 4-bit memory array circuit of 2 rows by 2 columns to which a semiconductor memory device according to the present invention is applied. The control gate electrode wiring 24 of each memory cell (Qij) is connected to a common selection line (Gi) for each row.
The drain regions 14 and charge amount control lines 27 are arranged as common drain lines (Dj),
Arranged as a charge amount control line (Epj). This drain line (Dj) is constituted by a bit line 26.
The source terminal 13 of each memory cell (Qij) is connected to source lines (Si) arranged column by column or row by column.

Next, the selective write operation of the memory cell array of FIG. 3 will be explained with reference to the time chart of FIG. 4. For example, to selectively write information "1" into a certain memory cell (i, j), set the corresponding charge amount control line (EPj) to 0V, and set the uncorresponding charge amount control line (EPk) (k≠j) is set to 5V, and a 15V pulse is applied only to the corresponding selection line (Gi) of each selection line. At this time, electrons are injected into the floating gate of only the selected memory cell (i, j) according to the above-described principle, and information "1" is written. In addition, when selectively writing information "0" to cells (i, j), the corresponding selection line (Gi) is set to 0V, the uncorresponding selection line (Gk) (k≠i) is set to 5V, and the corresponding selection line (Gi) is set to 5V. Apply a 15V voltage pulse only to the electric charge control line (EPj). At this time, electrons are emitted from the floating gate of only the selected memory cell (i, j), and information "0" is written.

Although FIG. 3 shows the case of a 4-bit array, it goes without saying that the semiconductor memory device of the present invention can be expanded to include n-bits. Also, 2
A second silicon island may be provided between the first silicon islands so as to be shared by each of the first silicon islands.

Effects of the Invention As described above, according to the present invention, the charge amount control terminal area is completely surrounded by an insulating material, and there is no fear of the punch-through phenomenon or pn junction breakdown described above, and proportional reduction is possible. Since the semiconductor memory device has a structure that can be significantly miniaturized in accordance with the above-mentioned rules, it is possible to obtain a semiconductor memory device with high bit density and high read speed. Furthermore, according to the present invention, the floating gate transistor has a structure that is basically electrically rewritable with one transistor per memory cell, except that it has a charge amount control terminal region made of a second silicon island. Even higher bit density is possible.

In addition, if the first silicon island and the second silicon island are configured using single crystal control, this can be easily realized by applying SOS (silicon on silicon) technology, and in addition, an oxide film is formed on the single crystal. Forming a film has the advantage of good reliability in film quality because the film thickness can be easily controlled during manufacturing.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the structure of a conventional semiconductor memory device.
FIGS. 2a, b, and c show a semiconductor memory device according to an embodiment of the present invention, FIG. 2a is a plan view thereof, and FIG.
Figure b is a sectional view taken along the line B-B' in Figure 2a;
2c is a sectional view taken along the line C-C' in FIG. 2b, FIG. 3 is a memory cell array circuit diagram to which the semiconductor memory device of the present invention is applied, and FIG. 4 is a circuit diagram of the circuit shown in FIG. 3. This is a time chart to explain the operation. 11... Insulating substrate, 12... Active region, 13...
...Source region, 14...Drain region, 15...
First silicon island, 16... Insulating material, 17...
Second silicon island, 18... Charge amount control terminal region, 20... Floating gate electrode, 22... Insulating thin film.

Claims (1)

[Claims] 1. A semiconductor region in which a source region, an active region, and a drain region are formed, a first insulating layer formed on this semiconductor region, and a floating layer formed on this first insulating layer. a gate electrode, a conductive layer disposed on a part of the floating gate electrode via a second insulating layer and insulated from the semiconductor region with an insulator, and a conductive layer disposed on a part of the floating gate electrode and on the conductive layer. A third insulating layer is formed, and by being formed on the third insulating layer, a layer is formed on the laminated portion of the semiconductor region and the floating gate electrode, and a laminated portion of the conductive layer and the floating gate electrode. a control gate electrode disposed above, and performing charge exchange between the floating gate electrode and the conductive layer via the second insulating layer using a Fuaura-Nordheim type tunnel effect. A semiconductor memory device characterized in that the amount of charge in the floating gate electrode is controlled to provide a memory function. 2. The semiconductor memory device according to claim 1, wherein the semiconductor region and the conductive layer are both made of single crystal silicon. 3. The semiconductor memory device according to claim 1 or 2, wherein the conductive layer commonly controls the amount of charge applied to a plurality of floating gate electrodes. 4. The semiconductor memory device according to any one of claims 1 to 3, wherein the third insulating layer is thinner than the first insulating layer.