JPS6359634A - シミユレ−タ - Google Patents
シミユレ−タInfo
- Publication number
- JPS6359634A JPS6359634A JP61204890A JP20489086A JPS6359634A JP S6359634 A JPS6359634 A JP S6359634A JP 61204890 A JP61204890 A JP 61204890A JP 20489086 A JP20489086 A JP 20489086A JP S6359634 A JPS6359634 A JP S6359634A
- Authority
- JP
- Japan
- Prior art keywords
- time
- simulation
- signal
- processor
- start signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004088 simulation Methods 0.000 claims abstract description 32
- 238000012545 processing Methods 0.000 abstract description 13
- 230000001360 synchronised effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000004422 calculation algorithm Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61204890A JPS6359634A (ja) | 1986-08-29 | 1986-08-29 | シミユレ−タ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61204890A JPS6359634A (ja) | 1986-08-29 | 1986-08-29 | シミユレ−タ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6359634A true JPS6359634A (ja) | 1988-03-15 |
| JPH0533424B2 JPH0533424B2 (enrdf_load_stackoverflow) | 1993-05-19 |
Family
ID=16498090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61204890A Granted JPS6359634A (ja) | 1986-08-29 | 1986-08-29 | シミユレ−タ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6359634A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442772A (en) * | 1991-03-29 | 1995-08-15 | International Business Machines Corporation | Common breakpoint in virtual time logic simulation for parallel processors |
-
1986
- 1986-08-29 JP JP61204890A patent/JPS6359634A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442772A (en) * | 1991-03-29 | 1995-08-15 | International Business Machines Corporation | Common breakpoint in virtual time logic simulation for parallel processors |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0533424B2 (enrdf_load_stackoverflow) | 1993-05-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4851995A (en) | Programmable variable-cycle clock circuit for skew-tolerant array processor architecture | |
| JPH0548494B2 (enrdf_load_stackoverflow) | ||
| JP2001060219A (ja) | エミュレーションとシミュレーションを用いた設計検証のための方法および装置 | |
| US5006979A (en) | Phase synchronization system | |
| KR102148043B1 (ko) | 유연성 있는 테스트 사이트 동기화 | |
| US20060085157A1 (en) | Synchronization of multiple test instruments | |
| US6505149B1 (en) | Method and system for verifying a source-synchronous communication interface of a device | |
| JPS6359634A (ja) | シミユレ−タ | |
| CN116303165B (zh) | 多芯片同步系统及方法 | |
| JP2778547B2 (ja) | デジタル信号処理回路シミュレーション装置 | |
| JP2001229211A (ja) | 非同期回路の検証方法 | |
| JPH1173440A (ja) | エミュレーション装置 | |
| JPS6059441A (ja) | デ−タ制御回路 | |
| JPH021571A (ja) | 故障シミュレーション装置 | |
| JPH0371362A (ja) | 論理シミュレーション用並列計算機 | |
| JPH01195547A (ja) | 故障シミュレーション装置 | |
| SU1509901A1 (ru) | Устройство дл контрол цифровых устройств | |
| JPH0524546B2 (enrdf_load_stackoverflow) | ||
| JPS63291156A (ja) | 計算機間の処理の同期方式 | |
| JPS61186869A (ja) | シミユレ−タ | |
| JPH0418677A (ja) | デジタル回路のシミュレーション方式 | |
| JPS6014357A (ja) | プログラムテスト方式 | |
| JPS60233739A (ja) | クロツク制御装置 | |
| JPS6270958A (ja) | 入出力処理装置の試験方式 | |
| JP2000293553A (ja) | 出力同時動作検証方法及び検証システム |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |