JPS635918B2 - - Google Patents
Info
- Publication number
- JPS635918B2 JPS635918B2 JP54111702A JP11170279A JPS635918B2 JP S635918 B2 JPS635918 B2 JP S635918B2 JP 54111702 A JP54111702 A JP 54111702A JP 11170279 A JP11170279 A JP 11170279A JP S635918 B2 JPS635918 B2 JP S635918B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- printing
- paste
- hole
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 27
- 238000007639 printing Methods 0.000 claims description 16
- 238000010304 firing Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- DOIRQSBPFJWKBE-UHFFFAOYSA-N dibutyl phthalate Chemical compound CCCCOC(=O)C1=CC=CC=C1C(=O)OCCCC DOIRQSBPFJWKBE-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001856 Ethyl cellulose Substances 0.000 description 1
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 229920001249 ethyl cellulose Polymers 0.000 description 1
- 235000019325 ethyl cellulose Nutrition 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明は厚膜多層配線基板の製造方法、特にそ
の多層配線回路のスルーホールの形成方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thick film multilayer wiring board, and particularly to a method for forming through holes in the multilayer wiring circuit.
従来厚膜多層配線回路は基板の所定の位置に導
体ペーストを印刷焼成後、その導体上に所定の寸
法を有するスルーホールの形を残す如く絶縁ペー
ストを印刷焼成して絶縁層を形成し、その上に導
体ペーストを印刷し、焼成することにより多層配
線回路を作製していた。第１図は前記従来の多層
配線回路基板の製造方法を示すものであり、１は
基板を示し、該基板上に導体ペーストを印刷焼成
して導体２を形成し（第１図のａ）、前記導体２
上にスルーホールの巾ｘを有せしむる如く絶縁ペ
ーストを印刷、焼成して絶縁層４を形成し（第１
図のｂ）、その上に導体ペーストを印刷、焼成す
ることにより上部導体５を形成し、前記スルーホ
ールにより上下の導体２と５とが接続されるよう
にしている。（第１図のｃ）。 Conventionally, thick film multilayer wiring circuits are made by printing and firing a conductive paste at a predetermined position on a board, and then printing and firing an insulating paste so as to leave the shape of a through hole with a predetermined size on the conductor to form an insulating layer. A multilayer wiring circuit was produced by printing a conductive paste on top and firing it. FIG. 1 shows the conventional method for manufacturing the multilayer wiring circuit board, in which 1 indicates a substrate, and a conductor paste is printed and fired on the substrate to form a conductor 2 (a in FIG. 1). Said conductor 2
An insulating paste is printed on the top so as to have the width x of the through hole and fired to form an insulating layer 4 (first
b) in the figure, an upper conductor 5 is formed by printing and firing a conductor paste thereon, and the upper and lower conductors 2 and 5 are connected through the through hole. (c in Figure 1).
しかし乍ら印刷時に絶縁ペーストでスルーホー
ルの垂直面x′を形成することは不可能であり、謂
所印刷のだれｙが必然的に発生し、所定のスルー
ホールの寸法ｘに対し、実際得られるスルーホー
ル寸法はきわめて小さくなり、このため、特に微
少スルーホールを精度良く形成することは困難で
あつた。 However, it is impossible to form the vertical plane x' of the through hole with insulating paste during printing, and so-called printing sag y inevitably occurs, and the actual yield for a given through hole dimension x is impossible. The dimensions of the through-holes that can be formed have become extremely small, making it difficult to form particularly minute through-holes with high precision.
本発明は前記の欠点を改善せんがため、基板に
先づ導体ペーストで導体を印刷、焼成し、前記導
体上に所定の寸法を有するスルーホール形成部
を、高温焼成により酸化又は熱分解し消失する有
機物ペーストで印刷し、それから絶縁ペーストで
前記基板および導体上を覆う如く絶縁層を印刷
し、これを焼成することにより前記有機物ペース
トを消失させて絶縁層中に所定のスルーホールを
形成せしめ、前記絶縁層およびスルーホール上に
導体ペーストを印刷、焼成することにより基板上
の上下の二つの導体層を接続するようにしたもの
である。なお、前記有機物ペーストは通常の厚膜
印刷技術で用いられるペースト（とくに導体ペー
ストに適用する）であり、主としてエチルセルロ
ース、ポリビニルアルコール、ジブチルフタレー
トなどからなるものである。これらの成分は、い
ずれも高温において酸化、気化して残留物を残さ
ない物質である。 In order to improve the above-mentioned drawbacks, the present invention first prints a conductor using conductor paste on the substrate and fires it, and then oxidizes or thermally decomposes the through-hole forming part having a predetermined size on the conductor and disappears by firing at a high temperature. printing with an organic paste, then printing an insulating layer so as to cover the substrate and the conductor with an insulating paste, and baking this to eliminate the organic paste and form a predetermined through hole in the insulating layer, The two upper and lower conductor layers on the substrate are connected by printing and baking a conductor paste on the insulating layer and through holes. The organic paste is a paste used in normal thick film printing technology (particularly applicable to conductor pastes), and is mainly composed of ethyl cellulose, polyvinyl alcohol, dibutyl phthalate, and the like. All of these components are substances that oxidize and vaporize at high temperatures, leaving no residue.
次に本発明の一実施例を第２図について説明す
る。第２図において１は配線基板、２はその上に
印刷、焼成により形成した導体である。本発明に
おいては、前記導体２の上に所定の寸法ｘを有す
るスルーホール形成部３を高温では酸化又は熱分
解して消失する有機物ペーストにより印刷する
（第２図ｂ）。続いて前記スルーホール形成部３を
含む前記基板１および導体２の上部全面に所定の
寸法を有する絶縁層４を絶縁ペーストで印刷し、
これを焼成することにより、前記導体２上に印刷
したスルーホール用の有機物ペースト３を消失さ
せ、絶縁層４中にスルーホール３′を形成させる
（第２図ｃ）。このようにして正確な寸法のスルホ
ール３′を形成した後、その絶縁層４上に導体層
５を導体ペーストで印刷し、焼成して多層配線基
板を構成する。なお前記有機物ペーストで印刷す
るスルーホール形成部３にも印刷のダレ現象は表
れるが、スルーホールの寸法は元々極めて小さい
ので、ダレ寸法も極めて小さく、実用上問題とは
なり得ない。 Next, one embodiment of the present invention will be described with reference to FIG. In FIG. 2, 1 is a wiring board, and 2 is a conductor formed thereon by printing and firing. In the present invention, a through-hole forming portion 3 having a predetermined dimension x is printed on the conductor 2 using an organic paste that disappears by oxidation or thermal decomposition at high temperatures (FIG. 2b). Subsequently, an insulating layer 4 having predetermined dimensions is printed on the entire upper surface of the substrate 1 and the conductor 2 including the through-hole forming portion 3 using an insulating paste,
By firing this, the organic paste 3 for through holes printed on the conductor 2 disappears, and through holes 3' are formed in the insulating layer 4 (FIG. 2c). After forming the through-holes 3' with accurate dimensions in this way, a conductor layer 5 is printed with conductor paste on the insulating layer 4 and fired to form a multilayer wiring board. Note that printing sag phenomenon also appears in the through-hole forming portion 3 printed with the organic paste, but since the dimensions of the through-holes are originally extremely small, the sag dimensions are also extremely small and cannot be a problem in practice.
本発明は、前記の如く、配線基板に印刷、焼成
により設けた導体上に、上下の導体を接続するス
ルーホール形成部を印刷してスルーホール寸法を
確保し、しかる後絶縁層を印刷し、焼成すること
により前記スルーホール形成部を消失させてスル
ーホール形成し、しかる後その上に導体層を印
刷、焼成するようにしたので絶縁物層に穴をあけ
る工程が不用で、厚膜印刷技術のみで微少スルー
ホールを精度よく形成させることが出来る効果が
ある。 As described above, the present invention prints a through-hole forming part for connecting the upper and lower conductors on the conductor provided by printing and firing on the wiring board to ensure the through-hole dimension, and then prints an insulating layer, By firing, the through-hole forming part disappears and a through-hole is formed, and then a conductor layer is printed and fired on top of it, so there is no need for the process of drilling holes in the insulating layer, and thick film printing technology is used. This has the effect of allowing minute through holes to be formed with high accuracy using only a single step.
第１図は従来の多層配線基板の製造方法を示す
説明図、第２図は本発明多層配線基板の製造方法
を示す説明図である。
１…基板、２…導体層、３…スルーホール形成
部、３′…スルーホール形成部３の消失によつて
形成されたスルーホール、４…絶縁層、５…導体
層。
FIG. 1 is an explanatory diagram showing a conventional method for manufacturing a multilayer wiring board, and FIG. 2 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Conductor layer, 3...Through hole formation part, 3'...Through hole formed by disappearance of the through hole formation part 3, 4...Insulating layer, 5...Conductor layer.
Claims (1)
り酸化又は熱分解して消失する有機物ペーストに
てスルーホール形成部を印刷し、該スルーホール
形成部を含む下部導体上に絶縁層を印刷し、該絶
縁層を焼成することにより前記スルーホール形成
部を焼失させてスルーホールを形成することを特
徴とする厚膜多層配線基板の製造法。1. Printing a through-hole forming part on the lower conductor formed on the substrate with an organic paste that disappears by oxidation or thermal decomposition by high-temperature firing, printing an insulating layer on the lower conductor including the through-hole forming part, A method for manufacturing a thick film multilayer wiring board, characterized in that the through hole forming portion is burned out by firing the insulating layer to form a through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11170279A JPS5636200A (en) | 1979-09-03 | 1979-09-03 | Method of manufacturing thick film multilayer wired substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11170279A JPS5636200A (en) | 1979-09-03 | 1979-09-03 | Method of manufacturing thick film multilayer wired substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5636200A JPS5636200A (en) | 1981-04-09 |
| JPS635918B2 true JPS635918B2 (en) | 1988-02-05 |
Family
ID=14567983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11170279A Granted JPS5636200A (en) | 1979-09-03 | 1979-09-03 | Method of manufacturing thick film multilayer wired substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5636200A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0443170Y2 (en) * | 1987-05-08 | 1992-10-13 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5422574A (en) * | 1977-07-21 | 1979-02-20 | Fujitsu Ltd | Method of making ceramic multiilayer circuit substrate |
| JPS5570099A (en) * | 1978-11-21 | 1980-05-27 | Nippon Electric Co | Method of manufacturing high packing density package substrate |
-
1979
- 1979-09-03 JP JP11170279A patent/JPS5636200A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5422574A (en) * | 1977-07-21 | 1979-02-20 | Fujitsu Ltd | Method of making ceramic multiilayer circuit substrate |
| JPS5570099A (en) * | 1978-11-21 | 1980-05-27 | Nippon Electric Co | Method of manufacturing high packing density package substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0443170Y2 (en) * | 1987-05-08 | 1992-10-13 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5636200A (en) | 1981-04-09 |
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