JPS6355955A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6355955A JPS6355955A JP20100786A JP20100786A JPS6355955A JP S6355955 A JPS6355955 A JP S6355955A JP 20100786 A JP20100786 A JP 20100786A JP 20100786 A JP20100786 A JP 20100786A JP S6355955 A JPS6355955 A JP S6355955A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- fuse
- aluminum
- passivation film
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000005275 alloying Methods 0.000 claims description 2
- 238000002161 passivation Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 2
- 230000004927 fusion Effects 0.000 abstract 2
- 230000007547 defect Effects 0.000 description 3
- 238000007664 blowing Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に半導体基板上に設けられたヒ
ユーズを溶断することによってリダンダンシ回路を作動
せしめる半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device that operates a redundancy circuit by blowing a fuse provided on a semiconductor substrate.
従来、メモリーＩＣ等のりダンダンシ回路のヒユーズと
してポリシリコンが使われるのが一鍛的であり、このポ
リシリコンはＭＯＳトランジスタのゲート端子の形成と
同一工程で作られている。Conventionally, polysilicon has always been used as a fuse for redundancy circuits such as memory ICs, and this polysilicon is made in the same process as the gate terminal of a MOS transistor.
しかしながら、上述した従来の半導体装置はヒユーズが
ゲート端子と形成と同一工程で行なわれるため、比較的
厚いポリシリコンであり、このヒユーズをレーザ等で溶
断する場合に、容易に溶断することができず周辺部を破
損し不良を発生することが少なくないと云う欠点がある
。However, in the conventional semiconductor device described above, the fuse is formed in the same process as the gate terminal, so it is made of relatively thick polysilicon and cannot be easily blown out when the fuse is blown out with a laser or the like. The drawback is that peripheral parts are often damaged and defects occur.
本発明の目的は上述の欠点を除去し、ヒユーズに配線用
アルミニウムのアロイ防止としてアルミニウムの下に設
けられる配線用ポリシリコンを使用することで不良発生
の少ない半導体装置を提供することにある。 。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a semiconductor device with fewer defects by using wiring polysilicon provided under aluminum to prevent alloying of wiring aluminum in a fuse. .
本発明はヒユーズの溶断不良を防ぐためにリダンダンシ
回路用のヒユーズとして、アロイスパイク防止として配
線用のアルミニウムの下に敷かれる配線ポリシリコンを
使用することにより構成される。The present invention is constructed by using wiring polysilicon laid under aluminum wiring to prevent alloy spikes as a fuse for a redundancy circuit in order to prevent a fuse from blowing out.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。図において
半導体基板１の上部にフィールド絶縁領域２が形成され
、この上面にアルミニウムのアロイスパイク防止用の配
線ポリシリコン３が設けられていて、配線用アルミニウ
ム４が配線用ポリシリコン３の中央部を除いて両側に設
けられ、配線用アルミニウム４はパッシベーション膜５
で覆われている。この構造はパッシベーション膜を成長
したのち、選択エツチングでリダンダンシ回路のヒユー
ズの溶断部のパッシベーション膜を除去し、このあとパ
ッシベーション膜をマスクに配線用アルミニウムをエツ
チングすることによって得られる。FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, a field insulating region 2 is formed on the upper part of a semiconductor substrate 1, and a wiring polysilicon 3 for preventing aluminum alloy spikes is provided on the upper surface of the field insulation region 2, and a wiring aluminum 4 covers the central part of the wiring polysilicon 3. The wiring aluminum 4 is provided on both sides except for the passivation film 5.
covered with. This structure is obtained by growing a passivation film, removing the passivation film at the fuse blown part of the redundancy circuit by selective etching, and then etching aluminum for wiring using the passivation film as a mask.
以上説明したように本発明は、リダンダンシ回路用のヒ
ユーズが配線用の薄いポリシリコンにより作られている
ので、容易に溶断することができ、溶断不良の発生を少
なくすることができると云う効果がある。As explained above, the present invention has the advantage that since the fuse for the redundancy circuit is made of thin polysilicon for wiring, it can be easily blown and the occurrence of fusing defects can be reduced. be.
【図面の簡単な説明】
第１図は本発明の一実施例の断面図である。
１・・・・・・半導体基板、２・・・・・・フィールド
絶縁領域、３・・・・・・配線ポリシリコン、４・・・
・・・配線用アルミニウム、５・・・・・・パッシベー
ション膜。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of an embodiment of the present invention. 1...Semiconductor substrate, 2...Field insulation region, 3...Wiring polysilicon, 4...
... Aluminum for wiring, 5... Passivation film.
Claims (1)
ダンシ回路ヒューズが配線用アルミニウムのアロイ防止
としてこの配線用アルミニウムの下に設けられる配線用
のポリシリコンであることを特徴とする半導体装置。1. A semiconductor device having a redundancy circuit, wherein the redundancy circuit fuse is polysilicon for wiring provided under aluminum for wiring to prevent alloying of aluminum for wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20100786A JPS6355955A (en) | 1986-08-26 | 1986-08-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20100786A JPS6355955A (en) | 1986-08-26 | 1986-08-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6355955A true JPS6355955A (en) | 1988-03-10 |
Family
ID=16433947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20100786A Pending JPS6355955A (en) | 1986-08-26 | 1986-08-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6355955A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05259404A (en) * | 1991-12-18 | 1993-10-08 | Internatl Business Mach Corp <Ibm> | Micromechanical switch |
| US6876057B2 (en) * | 2001-09-13 | 2005-04-05 | Seiko Epson Corporation | Semiconductor devices including fuses and dummy fuses |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197874A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS59163859A (en) * | 1983-03-09 | 1984-09-14 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6065545A (en) * | 1983-09-21 | 1985-04-15 | Hitachi Micro Comput Eng Ltd | Manufacture of semiconductor device and the same device |
| JPS60113944A (en) * | 1983-11-25 | 1985-06-20 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1986
- 1986-08-26 JP JP20100786A patent/JPS6355955A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197874A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS59163859A (en) * | 1983-03-09 | 1984-09-14 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6065545A (en) * | 1983-09-21 | 1985-04-15 | Hitachi Micro Comput Eng Ltd | Manufacture of semiconductor device and the same device |
| JPS60113944A (en) * | 1983-11-25 | 1985-06-20 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05259404A (en) * | 1991-12-18 | 1993-10-08 | Internatl Business Mach Corp <Ibm> | Micromechanical switch |
| US6876057B2 (en) * | 2001-09-13 | 2005-04-05 | Seiko Epson Corporation | Semiconductor devices including fuses and dummy fuses |
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