JPS6355944A - Manufacture of chip carrier - Google Patents

Manufacture of chip carrier

Info

Publication number
JPS6355944A
JPS6355944A JP61200617A JP20061786A JPS6355944A JP S6355944 A JPS6355944 A JP S6355944A JP 61200617 A JP61200617 A JP 61200617A JP 20061786 A JP20061786 A JP 20061786A JP S6355944 A JPS6355944 A JP S6355944A
Authority
JP
Japan
Prior art keywords
recess
metal foil
resin substrate
chip
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61200617A
Other languages
Japanese (ja)
Inventor
Toru Higuchi
徹 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP61200617A priority Critical patent/JPS6355944A/en
Publication of JPS6355944A publication Critical patent/JPS6355944A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain a chip carrier which is superior in the reliability of mounting of an electronic part chip to a resin substrate by a method wherein a recessed place for mounting the electronic part chip is provided in the surface of the resin substrate and a metal foil with a bonding agent applied to its lower face is adhered on the bottom face of the recessed place. CONSTITUTION:A recessed place 3 is provided in the surface of a resin substrate 1 and a circuit 9 is formed. Such a metal foil 5 as a copper foil is bonded on the bottom part of the recessed place 3 through a bonding agent 4 and the bottom face of the recessed place is coated with the metal foil 5. A bonding agent is applied to the surface of the metal foil 5 and an electronic part 2 is adhered on the metal foil 5. The chip 2 is connected with the circuit 9 by performing wire-bondings 10.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、ＰＣＢタイプなどのチップキャリアの製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a chip carrier such as a PCB type.

［背景技術］ チップキャリアの樹脂基板に電子部品チップを実装する
場合、ワイヤーボンディングの作業性のために樹脂基板
に凹所を設けてこの凹所内に電子部品チップを収め、凹
所の底面に電子部品チップを接着剤で接着するようにし
ている。そして樹脂基板としては通常〃ラスエポキシ銅
張積層板など樹脂積層板が使用され、凹所の形成はミー
リング加工など機械加工で座ぐり切削することによって
なされるものであり、凹所内は樹脂基板の内部が露出さ
れた状態にあって凹所内に実装する電子部品チップに樹
脂基板の内部を通過する湿気が作用するおそれがある。[Background Art] When mounting an electronic component chip on a resin substrate of a chip carrier, a recess is provided in the resin substrate for wire bonding workability, the electronic component chip is housed in this recess, and an electronic component chip is mounted on the bottom of the recess. The component chips are glued together using adhesive. As the resin substrate, a resin laminate such as a laminated epoxy copper clad laminate is usually used, and the recess is formed by counterbore cutting using a mechanical process such as milling. Moisture passing through the interior of the resin substrate may act on the electronic component chip mounted in the recess with the interior exposed.

この場合には電子部品チップは湿気によって信頼性が著
しく低下されることになるために、従来より第２図（ａ
）に示すように座ぐり加工で樹脂基板１に凹所３を形成
したのちに、化学メッキ及び電気メッキによって銅など
の金属メッキを凹所３に施し、第２図（ｂ）に示すよう
に凹所３の内面がメッキ／［８で被覆されるようにして
いる。In this case, the reliability of the electronic component chip would be significantly reduced by moisture, so it has been conventionally shown in Figure 2 (a).
) As shown in Fig. 2(b), after forming a recess 3 in the resin substrate 1 by counterbore processing, metal plating such as copper is applied to the recess 3 by chemical plating and electroplating, as shown in Fig. 2(b). The inner surface of the recess 3 is coated with plating/[8.

しかし、メッキ層８が付着する樹脂基板１はｔｊ（脂に
よって形成されているためにメッキ層８の密着性が低く
、熱によってメッキ層８に膨れが生じてメッキ層８が樹
脂基板１の凹所３の内面から剥離されるおそれがあり、
樹脂基板１への電子部品チップ２の実装の信頼性が低い
という問題があった。また、凹所３は座ぐり加工で形成
されるためにその底面には凹凸が生じることになるが、
メッキ層８はこの凹凸に沿って形成されるためにメッキ
層８の表面には凹凸がそのまま表れ、この点においても
電子部品チップ２の実装の信頼性が低いものであった。However, since the resin substrate 1 to which the plating layer 8 is attached is formed of tj (grease), the adhesion of the plating layer 8 is low, and the plating layer 8 swells due to heat, causing the plating layer 8 to form a dent in the resin substrate 1. There is a risk of it peeling off from the inner surface of part 3.
There was a problem in that the reliability of mounting the electronic component chip 2 on the resin substrate 1 was low. In addition, since the recess 3 is formed by counterboring, the bottom surface will be uneven.
Since the plating layer 8 is formed along these irregularities, the irregularities appear as they are on the surface of the plating layer 8, and in this respect as well, the reliability of mounting the electronic component chip 2 is low.

［発明の目的］ 本発明は、上記の点に鑑みて為されたものであり、樹脂
基板への電子部品チップの実装の信頼性が優れたチップ
キャリアの製造方法を提供することを目的とするもので
ある。[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a chip carrier with excellent reliability in mounting electronic component chips on a resin substrate. It is something.

［発明の開示］ しかして本発明に係るチップキャリアの製造方法は、樹
脂基板１の表面に電子部品チップ２を実装するための凹
所３を切削形成し、下面に接着剤４を設けた金属箔５を
凹所３の底面に接着剤４によって貼って凹所３の底面を
金属箔５で被覆することを特徴とするものであり、凹所
３の底面を被覆するにあたって金属箔５を接着剤４で凹
所３の底面に貼り付けるようにしたことによって上記目
的を達成したものであって、以下本発明を実施例により
詳述する。[Disclosure of the Invention] According to the method for manufacturing a chip carrier according to the present invention, a recess 3 for mounting an electronic component chip 2 is formed on the surface of a resin substrate 1 by cutting, and an adhesive 4 is provided on the lower surface of the metal. The metal foil 5 is pasted on the bottom surface of the recess 3 with an adhesive 4 to cover the bottom surface of the recess 3 with the metal foil 5. The above object has been achieved by attaching the adhesive 4 to the bottom surface of the recess 3.The present invention will be described in detail below with reference to Examples.

樹上基板１はガラスエポキシ銅張積層板など樹脂積層板
によって形成されるもので、その表面の中央部に凹所３
が設けてあり、またプリント板加工による＠箔のエツチ
ングなどで表面に回路９が形成しである。凹所３はミー
リング加工などｆｉ？、ｆｉ加工で切削することによっ
て形成されるものである。このように樹脂基板１に凹所
３を切削加工したのちに、凹所３の底面に＠箔などの金
属Ｍ５を貼り付ける。金属箔５は凹所３の底面の大きさ
より若干小さい程度の寸法で用いられるものであり、第
１図（ａ）に示すように金属箔５の下面にはエポキシ樹
脂系などの接着剤４が塗布して設けである。The tree board 1 is formed of a resin laminate such as a glass epoxy copper clad laminate, and has a recess 3 in the center of its surface.
is provided, and a circuit 9 is formed on the surface by etching of @ foil by printed board processing. Is the recess 3 milled etc.? , is formed by cutting using fi processing. After cutting the recess 3 in the resin substrate 1 in this manner, a metal M5 such as @ foil is attached to the bottom surface of the recess 3. The metal foil 5 used has a size slightly smaller than the bottom surface of the recess 3, and as shown in FIG. 1(a), an adhesive 4 such as epoxy resin is applied to the bottom surface of the metal foil 5. It is applied and installed.

そして金属箔５を凹所３の底面に配して接着剤４を凹所
３の底面に密着させた状態で加圧・加熱することによっ
て、第１図（ｂ）のように凹所３の底面に接着剤４で金
属箔５を貼り付け、凹所３の底面を金属Ｍ５で被覆する
。金属箔５はこのように接着剤４による接着で樹脂基板
１の凹所３の底面に付着しているために密着性が高く、
熱によって膨れて剥離したりするおそれはない、また凹
所３の底面に凹凸があってもこの凹凸は接着剤４の層で
吸収され、凹凸が金属箔５の表面に影響を与えることな
く金属箔５の表面を平坦にすることができる。またａ（
脂基板１にはその下面から突出するように多数の端子ピ
ンが取り付けてあり、この端子ビンは回路９に電気的に
接続しである。Then, by placing the metal foil 5 on the bottom surface of the recess 3 and pressurizing and heating the adhesive 4 in close contact with the bottom surface of the recess 3, the recess 3 is sealed as shown in FIG. 1(b). A metal foil 5 is attached to the bottom surface with adhesive 4, and the bottom surface of the recess 3 is covered with metal M5. Since the metal foil 5 is thus attached to the bottom surface of the recess 3 of the resin substrate 1 by adhesion with the adhesive 4, its adhesion is high;
There is no risk of swelling and peeling due to heat, and even if there are irregularities on the bottom surface of the recess 3, these irregularities are absorbed by the layer of adhesive 4, and the irregularities do not affect the surface of the metal foil 5, and the metal The surface of the foil 5 can be made flat. Also a(
A large number of terminal pins are attached to the resin substrate 1 so as to protrude from its lower surface, and these terminal pins are electrically connected to a circuit 9.

しかしてチップキャリアとなる上記の樹脂基板１にＩＣ
など半導体チップ等の電子部品チップ２を搭載するにあ
たっては、凹所３の底部において金Ｊ！４箔５の表面に
エポキシ樹脂系などの接着剤を塗布し、この上に電子部
品チップ２を載置することによって接着剤で電子部品チ
ップ２を凹所３の底面の金属箔５に接着させることによ
っておこなう。このように電子部品チップ２を樹脂基板
１に搭載したのちに、第１図（ｃ）のように電子部品子
ツブ２と回路９との間にワイヤーボンブイジグ１０を施
して電子部品チップ２と回路９とを電気的に接続する。Therefore, an IC is placed on the above resin substrate 1 which becomes a chip carrier.
When mounting an electronic component chip 2 such as a semiconductor chip, place the metal J! 4 Apply an adhesive such as epoxy resin to the surface of the foil 5 and place the electronic component chip 2 on top of the adhesive, thereby bonding the electronic component chip 2 to the metal foil 5 on the bottom of the recess 3 with the adhesive. Do it by doing this. After mounting the electronic component chip 2 on the resin substrate 1 in this way, a wire bomb jig 10 is installed between the electronic component chip 2 and the circuit 9 as shown in FIG. 1(c). and the circuit 9 are electrically connected.

そして必要に応じて電子部品チップ２を封止する。Then, the electronic component chip 2 is sealed as necessary.

［発明の効果］ 上述のように本発明にあっては、樹脂基板の表面に電子
部品チップを実装するための凹所を切削形成し、下面に
接着剤を設けた金属箔を凹所の底面に接着剤によって貼
って凹所の底面を金属箔で被覆するようにしたので、金
属箔は接着剤による接着で凹所の底面に密着性高く付着
されることになって、金属箔が熱によって膨れて剥離し
たりするおそれはなく、しかも凹所の底面に凹凸があっ
てもこの凹凸は接着剤の層で吸収され、金属箔の表面に
凹凸が表れるおそれはないものであり、この結果電子部
品チップを凹所内において実装信頼性高く樹脂基板に取
り付けることができるものである。[Effects of the Invention] As described above, in the present invention, a recess for mounting an electronic component chip is formed on the surface of a resin substrate by cutting, and a metal foil with an adhesive provided on the lower surface is attached to the bottom of the recess. Since the metal foil was attached to the bottom of the recess with adhesive and covered with metal foil, the metal foil was adhered to the bottom of the recess with high adhesion due to the adhesive, and the metal foil was not exposed to heat. There is no risk of blistering and peeling, and even if the bottom of the recess is uneven, the adhesive layer absorbs the unevenness and there is no risk of unevenness appearing on the surface of the metal foil.As a result, the electronic A component chip can be mounted on a resin substrate within a recess with high mounting reliability.

【図面の簡単な説明】 ｆｔ５１図（ａＨｂ）（ｃ）は本発明の一実施例の一部
の断面図、第２図輸）（ｂ）は従来例の断面図である。 １は樹脂基板、２は電子部品チップ、３は凹所、４は接
着剤、５は金Ｍ箔である。BRIEF DESCRIPTION OF THE DRAWINGS Fig. ft51 (aHb) (c) is a sectional view of a part of an embodiment of the present invention, and Fig. 2 (b) is a sectional view of a conventional example. 1 is a resin substrate, 2 is an electronic component chip, 3 is a recess, 4 is an adhesive, and 5 is a gold M foil.

Claims (1)

【特許請求の範囲】[Claims] （１）樹脂基板の表面に電子部品チップを実装するため
の凹所を切削形成し、下面に接着剤を設けた金属箔を凹
所の底面に接着剤によって貼って凹所の底面を金属箔で
被覆することを特徴とするチップキャリアの製造方法。(1) A recess for mounting an electronic component chip is formed on the surface of a resin substrate by cutting, and a metal foil with an adhesive on the lower surface is pasted on the bottom of the recess with an adhesive to cover the bottom of the recess with the metal foil. 1. A method for manufacturing a chip carrier, the method comprising: coating a chip carrier with
JP61200617A 1986-08-26 1986-08-26 Manufacture of chip carrier Pending JPS6355944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61200617A JPS6355944A (en) 1986-08-26 1986-08-26 Manufacture of chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61200617A JPS6355944A (en) 1986-08-26 1986-08-26 Manufacture of chip carrier

Publications (1)

Publication Number Publication Date
JPS6355944A true JPS6355944A (en) 1988-03-10

Family

ID=16427352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61200617A Pending JPS6355944A (en) 1986-08-26 1986-08-26 Manufacture of chip carrier

Country Status (1)

Country Link
JP (1) JPS6355944A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5374365A (en) * 1976-12-15 1978-07-01 Toshiba Corp Semiconductor ceramic package
JPS6035543A (en) * 1983-08-08 1985-02-23 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5374365A (en) * 1976-12-15 1978-07-01 Toshiba Corp Semiconductor ceramic package
JPS6035543A (en) * 1983-08-08 1985-02-23 Oki Electric Ind Co Ltd Manufacture of semiconductor device

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