JPS63261778A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPS63261778A JPS63261778A JP9656087A JP9656087A JPS63261778A JP S63261778 A JPS63261778 A JP S63261778A JP 9656087 A JP9656087 A JP 9656087A JP 9656087 A JP9656087 A JP 9656087A JP S63261778 A JPS63261778 A JP S63261778A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- chip
- printed wiring
- board
- printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000011253 protective coating Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、エレクトロニクス用電子機器に用いるプリン
ト配線板に関し、とりわけ半導体チップを放熱よく実装
した構造に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a printed wiring board used in electronic equipment, and more particularly to a structure in which a semiconductor chip is mounted with good heat dissipation.
従来の技術
半導体チップを、プリント配線板に直接実装する方法と
して、フィルムキャリヤ、チップオンボードなどの技術
が現存する。フィルムキャリヤは、ポリイミドフィルム
のコスト高と、加工工程の複雑さから広（普及していな
い。そして放熱性の点でもよくない。またガラス布基材
板面のチップオンボードは、半導体チップ内のアルミニ
ウム電極の汚染を招き、信頼性上の問題がある。またチ
ップオンボードはチップ単独の特性検査をおこないに＜
（、半導体チップ搭載後の検査歩留まり低下によるコス
ト高を招来している。2. Description of the Related Art There are existing techniques for directly mounting semiconductor chips on printed wiring boards, such as film carrier and chip-on-board techniques. Film carriers are not widely used due to the high cost of polyimide film and the complexity of the processing process.They are also not very popular in terms of heat dissipation.In addition, chip-on-board with a glass cloth base plate is This leads to contamination of the aluminum electrodes, which poses reliability problems.In addition, chip-on-board does not require testing the characteristics of the chip alone.
(This has led to higher costs due to lower inspection yields after semiconductor chips are mounted.
発明が解決しようとする問題点
半導体チップのプリント配線板への装着を低いコストと
、検査可能の形で実装し、放熱性もよくしなければなら
ない。Problems to be Solved by the Invention It is necessary to mount a semiconductor chip on a printed wiring board at low cost and in a testable manner, and to improve heat dissipation.
問題点を解決するための手段
本発明は、片面または両面配線板の開口部に対して、電
子部品チップ搭載かつ同チップ部を樹脂被覆してなる金
属基体絶縁配線板を、前記開口部に蓋を形成するように
、上面下向きで当接し、互いの面対面の対向電極箇所を
はんだ付けした構造になしたプリント配線板で゛ある。Means for Solving the Problems The present invention provides a metal substrate insulating wiring board having an electronic component chip mounted thereon and having the chip portion coated with a resin, for the opening of a single-sided or double-sided wiring board, and covering the opening with a lid. This is a printed wiring board having a structure in which the upper surfaces thereof are brought into contact with each other facing downward, and the opposing electrodes on the opposite surfaces are soldered.
作用
本発明によると、電子部品チップ搭載部が金属基体絶縁
板上に形成され、放熱効果が大であると共に、同チップ
搭載部が樹脂被覆されているから、これを別のプリント
配線板に接続するとき、互いの配線電極部分を面対面で
はんだ付けする場合に、十分な保護作用をもっている。According to the present invention, the electronic component chip mounting part is formed on the metal base insulating board, which has a large heat dissipation effect, and since the chip mounting part is coated with resin, it can be connected to another printed wiring board. It has a sufficient protective effect when the wiring electrode parts are soldered face-to-face.
実施例
第１図は実施例プリント配線板の断面図、第２図はその
一部のチップ部分断面図である。Embodiment FIG. 1 is a sectional view of an embodiment printed wiring board, and FIG. 2 is a partial sectional view of a part of the chip.
半導体チップを、プリント配線板の小片上に、第２図に
示すような断面構造、すなわち、絶縁層１をもつアルミ
ニウム板２に銅導体３を配し、これに半導体チップ４を
グイボンドし、ついで、金属細線５でワイアボンドする
。次に、エポキシ樹脂の滴下とＣスティンへの硬化をお
こない、保護コート樹脂９を設け、これにより、一種の
チップキャリヤ形のプリント配線板となし、アルミニウ
ム金属板２の片面に半導体チップ４を搭載した構造にす
る。そして、他面を放熱面に用いる。この状態で、検査
機による特性検査を容易とする。次に、このチップキャ
リヤを第１図のように、半導体チップ取付側を孔７に向
けて、親プリント配線板８の孔部に蓋をする形で搭載す
る。半導体チップ及びそのワイアボンディング部の総合
高さは、親プリント板８の孔７の深さ内に設定する。通
常このスペースは０．１〜１．６ｍｍの範囲にある。親
プリント板８の表面配ｆｉ３と、半導体チップキャリヤ
の表層配線３′とは、面対面で当接し、はんだ６で接続
される。すなわち、他のチップ部品と同様に、又同時に
、はんだペースト印刷法によるリフロウソルダリングが
可能である。また、片面のアルミ面は放熱スペースとな
り、放熱フィンの取り付けにも利用できる。A semiconductor chip is placed on a small piece of a printed wiring board with a cross-sectional structure as shown in FIG. , and wire bond with a thin metal wire 5. Next, epoxy resin is dripped and cured on the C stain to provide a protective coating resin 9, thereby creating a type of chip carrier type printed wiring board, with a semiconductor chip 4 mounted on one side of the aluminum metal plate 2. structure. The other surface is used as a heat radiation surface. In this state, the characteristics can be easily inspected using an inspection machine. Next, as shown in FIG. 1, this chip carrier is mounted in the hole of the parent printed wiring board 8 with the semiconductor chip mounting side facing the hole 7 so as to cover the hole. The overall height of the semiconductor chip and its wire bonding portion is set within the depth of the hole 7 of the parent printed board 8. Typically this space is in the range 0.1-1.6 mm. The surface wiring fi3 of the main printed board 8 and the surface wiring 3' of the semiconductor chip carrier are in face-to-face contact and connected with solder 6. That is, reflow soldering using the solder paste printing method is possible in the same manner as and at the same time as with other chip components. Additionally, the aluminum surface on one side serves as a heat dissipation space and can be used to attach heat dissipation fins.
半導体チップ４として厚さ０．３ｎａｍ、１．６５Ｘ１
．３０＋＋＋＋ａワイア結線用のパッド中心間げき０
、２ ｍｍの接続用電極のものを、アルミニウム基板の
厚さ１．０ｍ、銅箔厚さ３５μ、絶縁層厚さ４０μに銀
めっき後、半導体のグイボンディングと１２本の金属細
線５でワイアボンディングをおこなう。As the semiconductor chip 4, the thickness is 0.3 nm, 1.65X1
．． 30++++a Wire connection pad center gap 0
, 2 mm connection electrodes were silver-plated on an aluminum substrate with a thickness of 1.0 m, a copper foil with a thickness of 35 μm, and an insulating layer with a thickness of 40 μm, and then wire-bonded with semiconductor glue bonding and 12 thin metal wires 5. will be carried out.
グイボンド用の無溶剤製銀ペイントは１６０℃３０分の
加熱硬化で十分に接着が保たれる。保護コート９用のエ
ポキシ樹脂ペイントを滴下し、１５０℃２時間の硬化後
、直径９Ｍ半球の高さを最大１．５鴫とする。Solvent-free silver paint for Guibond maintains sufficient adhesion when cured by heating at 160°C for 30 minutes. Epoxy resin paint for protective coat 9 is applied dropwise, and after curing for 2 hours at 150°C, the height of the 9M diameter hemisphere is set to a maximum of 1.5 degrees.
親プリント板８の孔７の直径は約１０ｍとする。半導体
チップの搭載面を下にして載置する。The diameter of the hole 7 in the parent printed board 8 is approximately 10 m. Place the semiconductor chip with its mounting surface facing down.
親プリント板８に設けた対向電極３には、はんだペース
ト６（錫／鉛 ６３／３７）の印刷がおこなわれており
、他のチップ部品１０の電極１１と同時に２１５℃、１
５〜２０秒の条件ではんだ接合する。はんだ接合後、孔
７の空隙部にシリコンペーストの如き熱伝導の良い材料
を充填する事も必要に応じておこなう。親プリント板８
として、アクセスホールのあるもの、又同じ孔に、半導
体チップを搭載した子プリント板を親プリント板の両面
から搭載する事も板厚によっては可能である。Solder paste 6 (tin/lead 63/37) is printed on the counter electrode 3 provided on the main printed board 8 at 215° C. at the same time as the electrode 11 of the other chip component 10.
Solder the joint for 5 to 20 seconds. After soldering, the voids in the holes 7 may be filled with a material with good thermal conductivity, such as silicone paste, if necessary. Main printed board 8
Depending on the board thickness, it is also possible to mount child printed boards with semiconductor chips on both sides of the main printed board in the same hole, or in the same hole.
発明の効果
半導体チップを載置する子プリント板が、親プリント板
から分離独立した形で用いられ、ボンディング用のめっ
き、ボッティング樹脂のドリッピングと加熱硬化の処理
がすでになされているので親プリント板に対する加工を
要しないのでコストメリットがある。子プリント板の上
面はアルミニウム板になっており、半導体チップの許容
電力を例えば０．２５Ｗから１．５Ｗに上昇する事がで
きる。アルミニウム板に放熱用フィンを付設すれば更に
２〜３Ｗの電力損失を許容することができるものになる
。Effects of the Invention The child printed board on which the semiconductor chip is placed is used separately from the parent printed board, and has already been subjected to plating for bonding, dripping of botting resin, and heat curing. There is a cost advantage since no processing is required for the plate. The upper surface of the child printed board is an aluminum plate, and the permissible power of the semiconductor chip can be increased from 0.25W to 1.5W, for example. If heat dissipation fins are attached to the aluminum plate, a further 2 to 3 W of power loss can be tolerated.
第１図は本発明の実施例断面図、第２図はその一部電子
部品の断面図である。
１・・・・・・絶縁層、２・・・・・・アルミニウム板
、３・・・・・・銅導体、４・・・・・・半導体チップ
、５・・・・・・金属細線、６・・・・・・はんだ、７
・・・・・・親プリント板の孔、８・・・・・・親プリ
ント板、９・・・・・・保護コート用樹脂、１０・・・
・・・チップ部品、１１・・・・・・チップ部品の電極
。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of some of its electronic components. DESCRIPTION OF SYMBOLS 1...Insulating layer, 2...Aluminum plate, 3...Copper conductor, 4...Semiconductor chip, 5...Metal thin wire, 6...Solder, 7
..... Holes in the main printed board, 8 ..... The main printed board, 9 ..... Resin for protective coating, 10 ....
... Chip parts, 11... Electrodes of chip parts.
Claims (1)
ップ搭載かつ同チップ部を樹脂被覆してなる金属基体絶
縁配線板を、前記開口部に蓋を形成するように、上面下
向きで当接し、互いの面対面の対向電極箇所をはんだ付
けした構造のプリント配線板。A metal base insulated wiring board having an electronic component chip mounted thereon and having the chip portion coated with a resin is brought into contact with the opening of the single-sided or double-sided wiring board with the upper surface facing downward so as to form a lid over the opening; A printed wiring board with a structure in which opposing electrodes are soldered to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62096560A JPH0770803B2 (en) | 1987-04-20 | 1987-04-20 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62096560A JPH0770803B2 (en) | 1987-04-20 | 1987-04-20 | Printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63261778A true JPS63261778A (en) | 1988-10-28 |
| JPH0770803B2 JPH0770803B2 (en) | 1995-07-31 |
Family
ID=14168430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62096560A Expired - Lifetime JPH0770803B2 (en) | 1987-04-20 | 1987-04-20 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770803B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5041461A (en) * | 1988-09-30 | 1991-08-20 | Lilly Industries Limited | Organic compounds and their use as pharmaceuticals |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49119159A (en) * | 1973-03-20 | 1974-11-14 |
-
1987
- 1987-04-20 JP JP62096560A patent/JPH0770803B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49119159A (en) * | 1973-03-20 | 1974-11-14 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5041461A (en) * | 1988-09-30 | 1991-08-20 | Lilly Industries Limited | Organic compounds and their use as pharmaceuticals |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0770803B2 (en) | 1995-07-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070731 Year of fee payment: 12 |