JPS6317547A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6317547A
JPS6317547A JP16268686A JP16268686A JPS6317547A JP S6317547 A JPS6317547 A JP S6317547A JP 16268686 A JP16268686 A JP 16268686A JP 16268686 A JP16268686 A JP 16268686A JP S6317547 A JPS6317547 A JP S6317547A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor element
wiring board
conductive circuit
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16268686A
Other languages
Japanese (ja)
Inventor
Naoki Nakano
中野 直記
Mamoru Kamiyama
上山 守
Hideji Kuwajima
秀次 桑島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP16268686A priority Critical patent/JPS6317547A/en
Publication of JPS6317547A publication Critical patent/JPS6317547A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve adhesive properties on hermetic sealing by loading a semiconductor element onto the upper surface of a connecting pad and joining a cover for coating and sealing a land, a pin and a conductive circuit and the semiconductor element with the outer circumferential section of a substrate without being brought into contact with these land, pin and conductive circuit. CONSTITUTION:Lands 12, a conductive circuit 3 and connecting pads 5 are formed to a flexible substrate, and through-holes A are shaped to the land sections, thus acquiring a flexible wiring board 2. A substrate is disposed onto the lower surface of the flexible wiring board. Through-holes B having diameters larger than the through-holes A are shaped to the substrate at positions corresponding to the through-holes A, and pins are penetrated into the through-holes A, B. The pins and the lands in the periphery of the through-holes A are fixed and connected electrically, a semiconductor element 7 is loaded onto the upper surfaces of the connecting pads, and a cover 8 is joined with the outer circumferential section of the substarte in order to cover and seal the lands, the pins and the conductive circuit and the semiconductor element without being brought into contact with these lands, pins and conductive circuit. Accordingly, adhesive properties on hermetic seal are improved.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device.

(従来の技術とその問題点) 従来、半導体素子をプリント配線板上に搭載するには、
セラミック製のチップキャリアもしくはセラミック製の
パッケージを介して搭載する方法が一般的であった。し
かし一般的に使用されている高アルミナ質セラミック(
以下セラミックとする)は誘電率が約9と高くこのため
近年の演算速度の超高速化においては信号遅れが大きい
ため好ましい材料ではなかった。一方ガラスエポキシ配
線板は誘電率が5程度で配線の浮遊容量による信号波形
のくずれはセラミックより少ないもののセラミックに比
べ耐熱性が低い、熱伝導率が低い。
(Conventional technology and its problems) Conventionally, in order to mount a semiconductor element on a printed wiring board,
The most common method was to use a ceramic chip carrier or a ceramic package. However, commonly used high alumina ceramics (
Ceramics (hereinafter referred to as ceramics) have a high dielectric constant of about 9, and therefore are not preferred materials because of the large signal delay in the recent ultra-high-speed calculations. On the other hand, glass epoxy wiring boards have a dielectric constant of about 5 and are less likely to distort signal waveforms due to stray capacitance of wiring than ceramics, but they have lower heat resistance and thermal conductivity than ceramics.

という欠点を有しており実装の高密度化には限界があっ
た。
This has the drawback that there is a limit to high density packaging.

一方シリコンチップをプリント配線板上に直接搭載する
方法も試みられているが、チップキャリアを介したもの
が殆んどであり入出力の端子数が多いものはピングリッ
ドアレイ型パッケージとなり前述のセラミックに起因す
る欠点はさけられない。
On the other hand, attempts have been made to mount a silicon chip directly onto a printed wiring board, but most of them are mounted via a chip carrier, and those with a large number of input/output terminals are packaged in a pin grid array type package. The drawbacks caused by this cannot be avoided.

これらの改良として特願昭59−133916号に示さ
れる半導体素子搭載用配線板があるが。
As an improvement on these, there is a wiring board for mounting semiconductor elements as shown in Japanese Patent Application No. 133916/1982.

しかしこのものは金属板の露出している部分が少ないた
め放熱効果が十分でなく、またパッケージ化した場合、
気密封止の察の接着性に問題が生じる。
However, because there are few exposed parts of the metal plate, the heat dissipation effect of this product is insufficient, and when packaged,
Problems arise with adhesion during hermetic sealing.

本発明は上記の欠点のない半導体装置を提供することを
目的とするものである。
The object of the present invention is to provide a semiconductor device free from the above-mentioned drawbacks.

(問題点を解決するための手段) 本発明者らは上記の欠点について種々検討した結果、半
導体素子搭載用配線板を用いた半導体装置の構造を下記
に示すように、フレキシブル基板にランド、導電回路お
よび接続パッドを形成し。
(Means for Solving the Problems) As a result of various studies on the above-mentioned drawbacks, the present inventors have developed a structure of a semiconductor device using a wiring board for mounting semiconductor elements as shown below. form circuits and connection pads.

さらにランドの部分に貫通孔(A)を設けてフレキシブ
ル配線板を得、ついで上記で得たフレキシブル配線板の
下面に上面および/又は下面に導電回路が形成された基
板(以上基板とする)を配設し。
Furthermore, a through hole (A) is provided in the land portion to obtain a flexible wiring board, and then a substrate (hereinafter referred to as a substrate) on which a conductive circuit is formed on the upper and/or lower surface of the flexible wiring board obtained above is placed on the lower surface of the flexible wiring board obtained above. Arranged.

前記貫通孔(4)に対応する位置の基板に貫通孔開よシ
直径がやや大きめな貫通孔(B)を形成し9貫通孔開お
よび貫通孔(Bl内にピンを貫通させ、ピンと貫通孔(
5)の周辺のランドとは半田、銀ろう等で固着して電気
的に接続させ、また接続パッドの上面に半導体素子を搭
載し、かつランド、ピンおよび導電回路と接することな
くこれらと半導体素子とを覆い封止するために蓋を基板
の外周部分に接合した構造としたところ、誘電率が5程
度でセラミック配線板に比べ低く、耐熱性および熱伝導
率がガラスエポキシ配線板に比べ高く、高発熱密度の素
子も搭載可能であることが確認された。また放熱効果も
優れ、パンケージ化した場合、気密封止の際の接着性に
おいても問題が生じないことを確認した。
A through hole (B) with a slightly larger diameter is formed in the substrate at a position corresponding to the through hole (4), and a pin is passed through the through hole (Bl) to form a through hole (B) with a slightly larger diameter. (
5) The surrounding lands are fixed and electrically connected with solder, silver solder, etc., and the semiconductor element is mounted on the top surface of the connection pad, and the semiconductor element is connected to the lands, pins, and conductive circuits without contacting them. When the lid was bonded to the outer periphery of the board to cover and seal the board, the dielectric constant was around 5, lower than that of a ceramic wiring board, and the heat resistance and thermal conductivity were higher than that of a glass epoxy wiring board. It was confirmed that elements with high heat generation density can also be mounted. It also has an excellent heat dissipation effect, and it was confirmed that there would be no problems with adhesion during hermetic sealing when it was made into a pancage.

本発明は上面にランド、導電回路および接続パッドが形
成された7レキシプル配線板の下面に基板が配設され、
フレキシブル配線板のランドの部分に設けられた貫通孔
■お工び貫通孔図に対応する位置の前記基板に設けられ
た貫通孔(B)内にピンを上面がランドの部分に接する
ように挿入固着し。
In the present invention, a substrate is disposed on the lower surface of a 7-lexiple wiring board on which lands, conductive circuits, and connection pads are formed on the upper surface,
Through-hole provided in the land part of the flexible wiring board ■ Insert the pin into the through-hole (B) provided in the board at the position corresponding to the through-hole diagram so that the top surface touches the land part. It sticks.

また接続パッドの上面には半導体素子が搭載され。In addition, a semiconductor element is mounted on the top surface of the connection pad.

かつランド、ピンおよび導電回路と接することなく、こ
れらと半導体素子とを覆い封止するための蓋を前記基板
の外周部分に接合してなる半導体装置に関する。
The present invention also relates to a semiconductor device in which a lid for covering and sealing lands, pins, and conductive circuits without contacting these and a semiconductor element is bonded to the outer peripheral portion of the substrate.

本発明におけるフレキシブル配線板とはポリイミドフィ
ルム、ポリエステルフィルム、ポリアミドイミドフィル
ム等の可撓性のある薄板にランド。
The flexible wiring board in the present invention is a land on a flexible thin board such as polyimide film, polyester film, polyamide-imide film, etc.

導電回路および接続パッドが形成され、さらにランドの
部分に貫通孔(3)が設けられたものを示す。
A conductive circuit and a connection pad are formed, and a through hole (3) is provided in the land portion.

本発明において用いられる基板は5紙、ガラス繊維等か
らなる織布、不織布などにエポキシ、フェノール等の樹
脂組成物を含浸、積層成形硬化せしめた紙エポキシ積層
板2紙フェノール積層板。
The substrates used in the present invention are 5 paper-epoxy laminates and 2-paper phenol laminates, which are made by impregnating a woven fabric or non-woven fabric made of paper, glass fiber, etc. with a resin composition such as epoxy or phenol, and then laminating and curing it.

ガラスエポキシ積層板等のプリント配線板材料が用途に
応じて使用され、その上面および/又は下面に導電回路
が形成される。
Printed wiring board materials such as glass epoxy laminates are used depending on the application, and conductive circuits are formed on the top and/or bottom surfaces thereof.

基板に形成される貫通孔(Blはフレキシブル配線板の
下面に配設されたとき貫通孔図に対応する位置に形成さ
れ、可撓性のある薄板に形成される貫通孔開の直径より
やや大きめの貫通孔(B)を形成することが好ましく、
また基板の貫通孔(B)の周壁に導電層を形成すればピ
ンと固着する場合、可撓性のある薄板に形成したランド
との固着に用いる材料と同じ材料を用いて固着できるの
で好ましい。
A through-hole formed in the substrate (Bl is formed at a position corresponding to the through-hole diagram when arranged on the bottom surface of a flexible wiring board, and is slightly larger than the diameter of a through-hole formed in a flexible thin plate. It is preferable to form a through hole (B) of
Further, it is preferable to form a conductive layer on the peripheral wall of the through hole (B) of the substrate, because when fixing the conductive layer to the pin, the same material used for fixing to the land formed on the flexible thin plate can be used for fixing.

ピンは、特殊な材質は必要とせずコパール。The pin does not require any special material; it is made of copal.

42合金、52合金等が用いられ、その長さは挿入して
固着する基板の下面よシ突出させるため。
42 alloy, 52 alloy, etc. are used, and the length is so that it protrudes from the bottom surface of the board to which it is inserted and fixed.

フレキシブル配線板と基板とを合わせた厚さより長いも
のを用いることが好ましく、突出長さは1=以上ちるこ
とが好ましい。
It is preferable to use one that is longer than the combined thickness of the flexible wiring board and the substrate, and it is preferable that the protrusion length is 1 or more.

ピンとフレキシブル配線板および基板との固着は半田、
銀ろう等を用いて固着することが好ましい。
The pins are fixed to the flexible wiring board and the board using solder.
It is preferable to fix it using silver solder or the like.

またピンと基板との固着は樹脂を用いて固着してもよく
、適用される樹脂としては、エポキシ樹脂、ポリイミド
樹脂等の熱硬化性樹脂、耐熱性熱可塑性樹脂などが用途
、使用条件において選択され用いられる。さらに本発明
ではこれらの樹脂にAI!N、BN等の熱伝導性の良い
フィラーを混入すれば、放熱性に優れるので好ましい。
In addition, the pins and the board may be fixed using a resin, and the applicable resins include thermosetting resins such as epoxy resins and polyimide resins, and heat-resistant thermoplastic resins, depending on the application and usage conditions. used. Furthermore, in the present invention, AI! is added to these resins. It is preferable to mix a filler with good thermal conductivity, such as N or BN, because it provides excellent heat dissipation.

蓋は、ランド、ピンおよび導電回路と接しないようにし
てこれらを覆い基板の外周部分で接合されるが、接続パ
ッドの上面ば搭載される半導体素子とは接触して覆うよ
うにしてもよく、また接しないようにして覆うようにし
てもよく制限はないが、半導体素子の上面と接するよう
にすれば放熱性に優れるので好ましい。
The lid covers the lands, pins, and conductive circuits so that they do not come in contact with them, and is bonded to the outer periphery of the substrate. However, the lid may contact and cover the semiconductor elements mounted on the top surface of the connection pads. Although there is no limitation, it may be covered without contacting the semiconductor element, but it is preferable to contact the upper surface of the semiconductor element because heat dissipation is excellent.

蓋の材質は、銅、銅合金等熱伝導性に優れた金属を用い
れば放熱性に潰れるので好ましい。また接合するための
材料としては、ろう材を用いて接合してもよく、シリコ
ン樹脂、ポリイミド樹脂。
It is preferable to use a metal with excellent thermal conductivity, such as copper or a copper alloy, as the material of the lid, since it can be collapsed for heat dissipation. Further, as a material for joining, a brazing material may be used for joining, silicone resin, polyimide resin.

エポキシ樹脂等耐熱性に優れた熱硬化性樹脂を用いて接
合してもよく用途、使用条件に応じ適した接合材料が用
いられる。
A thermosetting resin with excellent heat resistance such as an epoxy resin may be used for bonding, and a bonding material suitable for the purpose and usage conditions is used.

ランド、導電回路および接続バンドを形成する材料とし
ては、特に制限はないが9価格、熱伝導性などの点で鋼
を用いることが好ましい。例えば可撓性のある薄板、基
板の表面に銅箔を張り合わせたシ、めっき処理などの手
段で形成する。
Although there are no particular restrictions on the material for forming the lands, conductive circuits, and connection bands, it is preferable to use steel in terms of cost, thermal conductivity, and the like. For example, it may be formed using a flexible thin plate, a copper foil pasted on the surface of a substrate, or a plating process.

(作用) 本発明になる半導体装置は、フレキシブル配線板を形成
する材料としてポリイミドフィルム、ポリアミドイミド
フィルム等の可撓性のある薄板を用いるため誘電率がセ
ラミック配線板に比較して低くガラスエポキシ配線板と
ほぼ同一のものが得られる。
(Function) The semiconductor device of the present invention uses a flexible thin plate such as polyimide film or polyamideimide film as a material for forming the flexible wiring board, so the dielectric constant is lower than that of a ceramic wiring board, and glass epoxy wiring is used. You will get something almost identical to the board.

またフレキシブル配線板の下面に基板を配設するので基
板の導電回路により熱伝導率および放熱効果が良好にな
る。
Further, since the substrate is disposed on the lower surface of the flexible wiring board, the thermal conductivity and heat dissipation effect are improved due to the conductive circuit of the substrate.

さらに基板に蓋を接合することにより放熱効果がさらに
向上する。
Furthermore, by bonding the lid to the substrate, the heat dissipation effect is further improved.

(実施例) 以下実施例によシ本発明を説明する。(Example) The present invention will be explained below with reference to Examples.

実施例1 寸法30X30mmで厚さ0.254 mmのポリイミ
ドフィルムの片1ffiK厚さ18μmの銅箔を張り合
わせ、銅箔の上面にレジスト膜を形成し、エツチング、
レジスト膜の剥離を行ない、第1図に示すような導電回
路3.半導体素子を接合するための接続パッド5および
中央部(寸法8x811n)を除いた部分に直径0.6
 ff1mのランド12を形成し、かつ接続パッド5.
ラッド12および半導体素子が搭載される部分を除いた
部分にソルダレジスト(太陽インキ製造製、商品名FO
C800G)6を塗布し、ついで各ランド12の部分に
打ち抜き加工法により直径0.5 mmの貫通孔(A)
14を72個設けたフレキシブル配線板2を得た。
Example 1 A piece of polyimide film with dimensions of 30 x 30 mm and a thickness of 0.254 mm was laminated with a copper foil of 18 μm in thickness, a resist film was formed on the upper surface of the copper foil, and etching was performed.
The resist film is peeled off to form a conductive circuit 3 as shown in FIG. A diameter of 0.6 is provided in the area excluding the connection pad 5 for bonding the semiconductor element and the central part (dimensions 8 x 811n).
A land 12 of ff1m is formed, and a connection pad 5.
Solder resist (manufactured by Taiyo Ink Manufacturing, product name FO
C800G) 6 is applied, and then a through hole (A) with a diameter of 0.5 mm is formed in each land 12 by punching.
A flexible wiring board 2 was obtained in which 72 pieces of No. 14 were provided.

一方、第2図に示すように寸法4 Q X40mmで厚
さ1.0閣のガラス不織布コンポジット積層板の両面に
厚さ18μmの銅箔を張り合わせた両面銅張積層板1(
新神戸電機製、商品名B665)をフレキシブル配線板
2の下面に配設した場合、フレキシブル配線板2に設け
られた貫通孔(A)14と対応する位置に直径0.6 
mmの貫通孔(Blllを超硬ドリルで形成した。この
後鋼箔の上面にレジスト[1成し、エツチング、レジス
ト膜の剥離を行ない第2図に示すような導電層17.導
電回路18およびランド19を形成し、さらに下面の導
電回路18の部分および下面の隣接するランド19間に
前記と同じソルダレジスト13を塗布し。
On the other hand, as shown in Fig. 2, a double-sided copper-clad laminate 1 (a double-sided copper-clad laminate 1 (
When a hole (manufactured by Shin-Kobe Denki, product name B665) is placed on the bottom surface of the flexible wiring board 2, a diameter of 0.6
A through hole (Blll) with a diameter of mm was formed using a carbide drill. After that, a resist [1] was formed on the upper surface of the steel foil, etching was performed, and the resist film was peeled off to form a conductive layer 17, a conductive circuit 18 and a conductive circuit 18 as shown in FIG. Lands 19 are formed, and the same solder resist 13 as described above is applied between the conductive circuit 18 portion on the lower surface and between adjacent lands 19 on the lower surface.

ついで導電層17.上面の導電回路18およびランド1
9の部分にニッケルめっきを7μmの厚さに施した。
Then conductive layer 17. Conductive circuit 18 and land 1 on top surface
Part 9 was plated with nickel to a thickness of 7 μm.

次に第3図に示すようにフレキシブル配線板2の下面に
両面鋼張積層板1を配設し、しかる後直径が0.48m
mで一方の端部をくぎの頭状に加工した長さ6mmの5
2合金のネールへラドピン4を貫通孔(A)14および
貫通孔(Blllに挿入し、他の一方の端部(端子)を
下面に露出させた後、ネールへラドピン4とランド12
および導電層17とをSn:Pb=63 : 37の半
田で固着して半導体素子搭載用配線板を得た。この後第
4図に示すように接続パッド5と寸法3X4mmの半導
体素子7とを寸法0. I X 0. I X高さ0.
5 mmのSn:Pb=5:95の半円柱を用いて接合
した。
Next, as shown in FIG.
5 with a length of 6 mm and one end shaped like a nail head.
After inserting the rad pin 4 into the nail of the 2 alloy into the through hole (A) 14 and the through hole (Bllll) and exposing the other end (terminal) to the bottom surface, insert the rad pin 4 and the land 12 into the nail.
and the conductive layer 17 were fixed with a solder of Sn:Pb=63:37 to obtain a wiring board for mounting a semiconductor element. Thereafter, as shown in FIG. 4, the connection pads 5 and the semiconductor element 7 with dimensions of 3 x 4 mm are connected to each other with dimensions of 0. IX0. I x height 0.
Bonding was performed using a 5 mm semicircular cylinder of Sn:Pb=5:95.

一方第5図に示すように寸法60 X60mmで厚さ0
.5−の銅板の中央部に高さ1.3an、加工部の曲率
半径が0.5圓Rで寸法32X32mmの突起10を絞
り加工で形成し、外周を寸法39X39−の寸法に切断
して蓋8を得た。ついでワット浴で蓋80表面にニッケ
ルめっきを2μmの厚さに施した。
On the other hand, as shown in Figure 5, the dimensions are 60 x 60 mm and the thickness is 0.
.. A protrusion 10 with a height of 1.3 an and a radius of curvature of the processed part of 0.5 mm R and dimensions of 32 x 32 mm is formed in the center of the copper plate 5- by drawing, and the outer periphery is cut into dimensions of 39 x 39- to form a lid. I got 8. Next, nickel plating was applied to the surface of the lid 80 to a thickness of 2 μm using a Watt bath.

次に蓋8の一部を半導体素子7の上面に接触させ、かつ
蓋8の外周を前記の両面銅張積層板1の外周部分に合わ
せSn:Pb=63 : 37の半田9を用いて接合し
て第5図に示す半導体装置を得た。
Next, a part of the lid 8 is brought into contact with the upper surface of the semiconductor element 7, and the outer periphery of the lid 8 is aligned with the outer periphery of the double-sided copper-clad laminate 1 and bonded using solder 9 of Sn:Pb=63:37. As a result, a semiconductor device shown in FIG. 5 was obtained.

得られた半導体装置について熱伝導率および誘電率を測
定したところ、半導体素子を搭載した部分の熱伝導率は
、 o、 4s cal/cm ・秒 ’cで半導体素
子から発生する熱を下面および上面に放熱することが出
来、誘電率は、5.5でガラスエポキシ配線板とほぼ同
一であった。なお熱伝導率および誘電率の測定は、JI
S  C2141に準じて行なった。
When we measured the thermal conductivity and dielectric constant of the obtained semiconductor device, we found that the thermal conductivity of the part where the semiconductor element was mounted was 0, 4 s cal/cm · sec 'c, and the heat generated from the semiconductor element was transferred to the bottom and top surfaces. The dielectric constant was 5.5, which was almost the same as that of a glass epoxy wiring board. The thermal conductivity and dielectric constant are measured by JI
It was carried out according to SC2141.

また半導体素子搭載用配線板から露出した72本のネー
ルへラドピン4を無負荷挿入用ソケット(図示せず)K
挿入後レバーを操作してネールヘッドピン4をソケット
内ではさみ込んで固定した。
In addition, a socket (not shown) K for inserting RAD pins 4 with no load into the 72 nails exposed from the wiring board for mounting semiconductor elements.
After insertion, the nail head pin 4 was inserted and fixed in the socket by operating the lever.

ネールへラドピン4をはさみ込んだときネールへラドピ
ン4に歪が発生するが、このネールへラドピン4をはさ
み込む操作を100回繰り返し行なってもフレキシブル
配線板2と半導体素子7とを接合している半田柱には亀
裂などの破断は発生しなかった。
When the Rad pin 4 is inserted into the nail, distortion occurs in the Rad pin 4, but even if this operation of inserting the Rad pin 4 into the nail is repeated 100 times, the flexible wiring board 2 and the semiconductor element 7 are still bonded. No cracks or other fractures occurred in the solder pillars.

さらに上記で得た半導体装置を、120℃、2気圧(ゲ
ージ圧)t 100時間の条件でプレツシャククカー試
験を行なったが蓋内の導電回路の断線、腐食等は見られ
なかった。
Further, the semiconductor device obtained above was subjected to a pressurization test at 120° C. and 2 atm (gauge pressure) for 100 hours, but no breakage or corrosion of the conductive circuit inside the lid was observed.

比較例1 寸法40X40mmで厚さ1.0 onのガラス不織布
コンポジット積層板の両面に厚さ18μmの銅箔を張り
合わせた両面銅張積層板(新神戸電機製。
Comparative Example 1 A double-sided copper-clad laminate (manufactured by Shin-Kobe Electric Machinery Co., Ltd.) in which copper foil with a thickness of 18 μm was laminated on both sides of a glass nonwoven fabric composite laminate with dimensions of 40×40 mm and a thickness of 1.0 on.

商品名E665 )の中央部(寸法8X8mm)を除い
た部分に2.54mm間隔で超硬ドリルで直径0.6−
の貫通孔を72個設けた。この後エツチドフォイル法に
より両表面と貫通孔内に10±2μmの厚さに銅めっき
を施し9貫通孔内に導電層を形成し、ついで表面にレジ
スト膜の形成、エツチング。
(product name: E665) except for the center part (dimensions 8 x 8 mm) with a carbide drill at 2.54 mm intervals.
72 through holes were provided. Thereafter, copper plating was applied to both surfaces and the through holes to a thickness of 10±2 μm using the etched foil method, a conductive layer was formed in the through holes 9, and then a resist film was formed on the surfaces and etched.

レジスト膜の剥離を行ない上面に所定の導電回路。The resist film is peeled off and a predetermined conductive circuit is formed on the top surface.

接続パッドおよび上、下面の貫通孔の外周に幅0、3 
anのランドを形成し、これらを導通させた基板を得た
Width 0, 3 on the outer periphery of the connection pad and through holes on the upper and lower surfaces.
A substrate was obtained in which lands of an were formed and these were made electrically conductive.

次に上記の貫通孔にネールへラドピンを挿入し。Next, insert the rad pin into the nail through the above through hole.

ネールヘッドピンと上記基板とをSn:Pb=63:3
7の半田で固着した。以下実施例1と同様の方法で接続
パッドと半導体素子とを接合した。
The nail head pin and the above board are Sn:Pb=63:3.
It was fixed with solder number 7. Thereafter, the connection pads and the semiconductor element were bonded together in the same manner as in Example 1.

この後実施例1と同様の方法で熱伝導率および誘電率を
測定したところ、誘電率は5.2でガラスエポキシ配線
板とほぼ同一であったが、半導体素子を搭載した部分の
熱伝導率は0.07 cat/ am・秒・℃で半導体
素子から発生する熱は、上面から放熱することが出来る
が、下面からの放熱が悪く良好な放熱性は得られなかっ
た。
After that, when the thermal conductivity and dielectric constant were measured in the same manner as in Example 1, the dielectric constant was 5.2, which was almost the same as that of the glass epoxy wiring board, but the thermal conductivity of the part where the semiconductor elements were mounted was The heat generated from the semiconductor element at a rate of 0.07 cat/am·sec·° C. can be radiated from the top surface, but heat radiation from the bottom surface is poor and good heat radiation performance cannot be obtained.

また実施例1と同様の方法でネールへラドピンに歪を繰
り返し加えたところ5回縁シ返しただけで基板と半導体
素子とを接合している半田柱に亀裂が入り電気的な導通
が確保出来なかった。
Furthermore, when strain was repeatedly applied to the rad pin to the nail in the same manner as in Example 1, cracks appeared in the solder pillars connecting the substrate and the semiconductor element after only 5 times of edge bending, and electrical continuity could not be ensured. There wasn't.

なお比較例1では蓋を接合する前に欠点が生じたので、
蓋を基板の外周部分に接合する作業は行なわなかった。
In addition, in Comparative Example 1, a defect occurred before the lid was joined, so
No work was performed to bond the lid to the outer peripheral portion of the substrate.

なお本発明の実施例では上面が平坦な形状の蓋を用いた
例で説明したが、第6図に示すように上部に折曲部15
を形成し九M16を用いれば、放熱効果がさらに優れる
ので好ましい。
In the embodiment of the present invention, the lid has a flat top surface, but as shown in FIG.
If 9M16 is used, the heat dissipation effect will be even better, so it is preferable.

(発明の効果) 本発明になる半導体装置は、誘電率、熱伝導率。(Effect of the invention) The semiconductor device according to the present invention has a dielectric constant and a thermal conductivity.

放熱効果および機械的強度に優れ、蓋を接合する際の接
着性においても問題がないなどの効果を奏する半導体装
置である。゛
This semiconductor device has excellent heat dissipation effects and mechanical strength, and has no problems with adhesion when joining the lid.゛

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図、第3図、第4図および第5図は本発明
の一実施例における半導体装置の製造作業状態を示す断
面図、第6図は本発明の他の一実施例になる半導体装置
に用いられる蓋の断面図である。 符号の説明 1・・・両面鋼張積層板 2・・・フレキシブル配線板
3・・・導電回路    4・・・ネールへラドピン5
・・・接続ハツト   6・・・ソルダレジスト7・・
・半導体素子   8・・・蓋 9・・・半1)    10・・・突起11・・・貫通
孔(B)    12・・・ランド13・・・ソルダレ
ジスト 14・・・貫通孔(3)15・・・折曲部  
  16・・・蓋17・・・導電層     18・・
・導電回路19・・・ランド 嘱/固 ′$ 3 図
1, 2, 3, 4, and 5 are cross-sectional views showing the state of manufacturing work of a semiconductor device in one embodiment of the present invention, and FIG. 6 is another embodiment of the present invention. FIG. 2 is a cross-sectional view of a lid used in a semiconductor device. Explanation of symbols 1... Double-sided steel clad laminate 2... Flexible wiring board 3... Conductive circuit 4... Rad pin to nail 5
...Connection hat 6...Solder resist 7...
・Semiconductor element 8...Lid 9...Half 1) 10...Protrusion 11...Through hole (B) 12...Land 13...Solder resist 14...Through hole (3) 15 ...Bending part
16... Lid 17... Conductive layer 18...
・Conductive circuit 19...Rand 嘱/K'$ 3 Figure

Claims (1)

【特許請求の範囲】[Claims] 1、上面にランド、導電回路および接続パッドが形成さ
れたフレキシブル配線板の下面に、上面および/又は下
面に導電回路が形成された基板が配設され、フレキシブ
ル配線板のランドの部分に設けられた貫通孔(A)およ
び貫通孔(A)に対応する位置の前記基板に設けられた
貫通孔(B)内にピンを上面がランドの部分に接するよ
うに挿入固着し、また接続パッドの上面には半導体素子
が搭載され、かつランド、ピンおよび導電回路と接する
ことなく、これらと半導体素子とを覆い封止するための
蓋を前記基板の外周部分に接合してなる半導体装置。
1. A substrate with a conductive circuit formed on the top and/or bottom surface is disposed on the bottom surface of a flexible wiring board with a land, a conductive circuit, and a connection pad formed on the top surface, and a substrate is provided on the land portion of the flexible wiring board. A pin is inserted and fixed into the through hole (A) provided in the through hole (A) and the through hole (B) provided in the board at a position corresponding to the through hole (A) so that the top surface is in contact with the land portion, and the top surface of the connection pad is A semiconductor device in which a semiconductor element is mounted on the substrate, and a lid is bonded to the outer periphery of the substrate to cover and seal the semiconductor element and the semiconductor element without contacting the lands, pins, and conductive circuits.
JP16268686A 1986-07-10 1986-07-10 Semiconductor device Pending JPS6317547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16268686A JPS6317547A (en) 1986-07-10 1986-07-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16268686A JPS6317547A (en) 1986-07-10 1986-07-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6317547A true JPS6317547A (en) 1988-01-25

Family

ID=15759370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16268686A Pending JPS6317547A (en) 1986-07-10 1986-07-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6317547A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03165484A (en) * 1989-11-24 1991-07-17 Tokai Carbon Co Ltd Flexible sheet type element and its manufacture
US5925851A (en) * 1996-10-28 1999-07-20 Asmo Co., Ltd. Lead wire guiding structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03165484A (en) * 1989-11-24 1991-07-17 Tokai Carbon Co Ltd Flexible sheet type element and its manufacture
US5925851A (en) * 1996-10-28 1999-07-20 Asmo Co., Ltd. Lead wire guiding structure

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