JPS6354875A - Run length encoder - Google Patents

Abstract

PURPOSE:To improve a processing speed by performing a run length encoding processing under a parallel state without converting the input data of a parallel input into serial data. CONSTITUTION:A gate circuit 3, the first multiplexer 4, a means 7 for generating a data load flag, an adder 8, the second multiplexer 10, a run length register 9, an output register 11 and a control circuit 1 are provided. An output signal C goes to '1' and the multiplexer 10 selects the output of the adder 8, and then, an output signal D goes to '0', the output register 11 is not operated nor the output data of the adder 8 is latched. Since an output signal E goes to '0', a color flag register 2 is not operated but holds a preceding color flag. Since can output signal F goes to '0', the multiplexer 4 selects the output side of an Ex-OR3 and an output signal G goes to '0', so that the load flag is brought into '0'. Thereby, the run length encoding processing can be executed in parallel and the processing speed can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a run-length encoding device, and particularly to a run-length encoding device that increases the encoding speed.

(Prior Art) A conventional run-length encoding device will be explained with reference to FIG.

The data input Din is sent, for example, as an 8-bit parallel signal. This parallel data input D1n is converted into a serial signal by the parallel-serial conversion circuit 21 and input to the change point detection circuit 22. The change point detection circuit 22 is a circuit that detects the point where the serial data changes from 0 to 1 or from 1 to 0, and the output of this circuit 22 is manually input as a control circuit to a counter 23 that counts the number of input bits.

When the change point detection signal is input from the change point detection circuit 22, the counter 23 transfers the output of the counter 23 to the register 24.
It is reset at the same time as sending the data. Therefore, data indicating how many consecutive bits of 0 or 1 data are latched into the register 24. As a result, register 24
A run-length encoded signal will be output from.

(Problems to be Solved by the Invention) As described above, the conventional apparatus performed run-length encoding processing after converting parallel data into serial data, so the run-length encoding processing was performed bit by bit. , there was a problem that the processing speed was slow.

The purpose of the present invention is to eliminate the problems of the conventional device described above,
An object of the present invention is to speed up processing by providing a device that can perform run-length encoding processing on input parallel data as it is without converting it into serial data.

(Means and operations for solving the problem) In order to solve the above problem, the present invention provides a gate circuit that takes an exclusive OR of parallel input data and a color flag output from a color flag register. , a first multiplexer for selecting the output of the gate circuit and modified data; means for generating a data load flag; and addressing parallel data with the data load flag added to the MSB side of the output of the first multiplexer. a ROM table that outputs first and second run length data, run length valid data, a next data request and the modified data; an adder that receives the first run length data as one input; a second multiplexer whose inputs are the run-length data of the adder and the output of the adder; and a run-length filter connected to the output side of the second multiplexer and whose output is connected to the other input terminal of the adder. A register, an output register connected to the output side of the adder, run length valid data and next data request output from the ROM table are input, and a control signal according to these states is sent to the color flag register. , a first multiplexer, a data load flag generating means, a second multiplexer, and a control circuit for outputting to an output register.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 1 is a control circuit consisting of a microcomputer, etc., 2 is a color flag register that outputs a color flag controlled by a signal E output from the control circuit 1, and 3 is an exclusive connection between input data and the color flag. This is a gate circuit (hereinafter referred to as an Ex-OR circuit) that calculates a logical sum. 4 is a multiplexer controlled by the signal F from the control circuit 1, and 6 is a ROM table.

The ROM table 6 has the following data at the address specified by manual data. That is,
First run length data 6as second run length data 6b, run length valid bit data 6 C% Netast data request data 6d and correction data (Revi
sed Data) 6 holds each data of e.

7 is controlled by the signal G output from the control circuit 1, and outputs 0 when input data comes through the multiplexer 4, and outputs 1 when modified data, which will be described later, comes.
8 is an adder that adds the output RLI of the first run length data 6a and the data stored in the run length register 9; 10 is a signal C output from the control circuit 1; This is a multiplexer that selects the output RL2 of the second rungless data 6b and the output data of the adder 8.

Further, 11 is an output register that temporarily stores the output data of the adder 8.

Here, the color flag register 2, data load flag generator 7, run length register 9, and output register 11 operate in synchronization with a clock (not shown).

Next, the operation of this embodiment having the above configuration will be explained.

Note that FIG. 2 shows a diagram showing the relationship between the human output signals of the control circuit 1, and FIG. 3 shows a diagram showing an example of the operation of this embodiment.

First, before clock 0 is input, 0 is stored in run length register 9.

In this state, if a color flag of 0 is output from the color flag register 2 and input data Di of 8 bits 0J)001110 (see Figure 3) is input, then
The output of the Ex-OR circuit 3 becomes 00001110. When the data passes through the multiplexer 4, the data load flag generator 7 outputs a flag of 0, which is added to the MSB of the input data Di, leading to 9-bit data to the ROM table 6. In other words, (
) 9-bit ROM input data 000001
110 is led to the ROM table 6.

The first run length data 6a of the ROM table 6 is
When the MSB of the input data is 0, a binary number is output that is the number of consecutive 0s from the MSB to the LSB minus 1. On the other hand, when the MSB of the input data is 1, the 0 that appears for the first time on the LSB side is output. Starting from 0, the number of consecutive 0s from the O toward the LSB is output as a binary number. For this reason,
In the operation example currently being considered, the first run length data 6a outputs an output RLI of 100(-4).

The second run length data 6b outputs the number of 1's in a binary number when all 1's are on the LSB side from the consecutive O's. In the example we are considering now, the LSB from the consecutive 0s is
Since all sides are not 1, 0 data is output.

The run length valid bit data 6c is the continuous 0
If there is a 1 on the LSB side, output 1, LSB
If there is no 1 on the side, 0 is output.

Next data request data 6d is LS from consecutive O
If the B side is all 1, or if the LSB of the consecutive O's is the θ-th bit, 1 is output, and if this condition is not met, 0 is output.

Furthermore, when the output of the netast data request data 6d is O, the correction data 6e sets the sequence of O corresponding to the output of the first unlength data 6a to 1, and the LSB
The modified data created by inverting all the bits on the side is stored.

In this specific example, this modified data is 111.100
It becomes 01.

Adder 8 outputs RLI value 4 and run length register 9
Add the data 0 stored in .

This result is latched into output register 11 at clock 0.

Also, the value 0 of the output RL2 coming through the multiplexer 10 is latched into the run length register 9 by the clock 0.

At this time, since the input signals A and B to the control circuit 1 are 1 and 0, respectively, the output signals CG are as shown in FIG. That is, the multiplexer 10 is outputted with a signal C that selects the output RL2 of the second run length data 6b.

Further, a signal 1 for inverting the output is output to the color flag register 2, a signal for selecting corrected data is output to the multiplexer 4, and a signal for setting the load flag to 1 is output to the data load flag generator 7. be done.

As a result, ROM table 6 contains correction data 11110.
Data in which 1 is added to the MSSB of 001 is input, the output RLI of the first run length data 6a is 3, the output RL2 of the second run length data 6b is 1, the output A of the RL valid data 6c is 1, Output B of the next data request 6e becomes 1.

Next, when the second clock 1 is input, the output register 11 receives the value 3 of the output RLI and the run length register 9.
The run length register 9 latches the value added to the value 0 held in the output RL2, and the run length register 9 latches the value of the output RL2. As a result, the output register 11 latches the value 3, and the run length register 9 latches the value 1.

At this time, since the inputs A and B of the control circuit 1 are each 1.1, the output of the control circuit 1 is as shown in FIG.

That is, the multiplexer 10 selects the output RL2 of the second run length data 6b. The color flag register 2 also receives a signal E for inverting the color flag,
Multiplexer 4 selects the output of Ex-OR circuit 3,
The data load flag generator 7 outputs a load flag 0.

The next input data Di, i.e. ooooooooo is Ex
- When input to one terminal of OR3, ROM table 6 contains 9-bit data ooooooo with 0 added to the MSB side output from data load flag generator 7.
ooo enters. Then, the output RLI of the first run-length data 6a becomes 8, the output RL2 of the second run-length data 6b becomes 01, the RL valid data A becomes 0, and the output B of the next data request 6d becomes 1. Therefore, the input data A and B of the control circuit 1 are each 0.1,
The output CG of the control circuit 1 is as shown in FIG.

That is, since the output signal C becomes 1, the multiplexer 10 selects the output of the adder 8, and since the output signal C becomes 0, the output register 11 does not operate and does not latch the output data of the adder 8. On the other hand, since the output signal E becomes 0, the color flag register 2 does not operate and holds the previous color flag. Since the output signal F is 0, the multiplexer 4 selects the output side of Ex-OR3, and the output signal G is 0.
Therefore, set the load flag to 0.

As a result, at the third clock 2, new data is not latched in the output register 11, and the previous data 3
remains held, while the value 9, which is the output of the adder 8, is latched in the run length register 9.

Thereafter, when similar operations are repeated sequentially, the input data 000011100000 as shown in FIG.
0000 11110001 11111111 11
111000..., the data in the output register 11 is 4,3.9°4.3.14.・・・・・・
・The encoded run length is obtained.

As described above, according to this embodiment, run-length encoding processing can be performed in parallel, and processing speed can be significantly increased compared to conventional serial processing.

In the above embodiment, for example, the third run length data is created in the ROM table 6, and the ROM
By increasing the output of table 6, the processing speed can be further increased. Also, if you change the contents of the data in ROM table 6, the run length can be detected at the same time as enlargement and
You can also add a shrink function.

(Effects of the Invention) As described above, according to the present invention, run-length encoding processing can be performed in the parallel state without converting parallel input input data into serial data. This has the great effect of significantly increasing processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a diagram illustrating the operation of the embodiment described above, and FIG. 4 is a block diagram illustrating an example of a conventional run-length encoding device. 1...Control circuit, 2...Color flag register, 4.10...Multiplexer, 6...ROM
Table, 7...Data load flag generator, 8
... Adder, 9 ... Run length register, 1
1...Output register

Claims (3)

[Claims] (1) A gate circuit that takes the exclusive OR of the parallel input data and the color flag output from the color flag register, a first multiplexer that selects the output of the gate circuit and modified data, and a data load flag. the first and second run-length data, run-length valid data, next data request and the correction using parallel data with the data load flag added to the MSB side of the output of the first multiplexer as an address; a ROM table that outputs data; an adder that receives the first run-length data as one input; a second multiplexer that receives the second run-length data and the output of the adder; a run-length register connected to the output side of the second multiplexer and whose output is connected to the other input terminal of the adder; an output register connected to the output side of the adder; and an output from the ROM table. The run length valid data and the next data request are input, and control signals corresponding to these states are sent to the color flag register, the first multiplexer,
A run-length encoding device comprising a data load flag generating means, a second multiplexer, and a control circuit for outputting to an output register, and performing run-length encoding in parallel. (2) When the MSB of the data input to the ROM table is 0, the first run length data is
It is the number obtained by subtracting 1 from the number of consecutive 0s toward the LSB, and on the other hand, when the MSB is 1, it is the number of consecutive 0s counted starting from the bit where 0 appears for the first time on the LSB side. A run-length encoding device according to claim 1, characterized in that: (3) The second run length data represents the number of 1's when all 1's are on the LSB side from the consecutive 0's, and 0 when all the LSB's from the consecutive 0's are not 1's.
The run-length encoding device according to claim 2, characterized in that the run-length encoding device is configured to represent the following.