JPH08314695A - Digital adding circuit - Google Patents

Abstract

PURPOSE: To perform secure data clipping by a circuit of simple constitution as to the digital adding circuit which is used as one constituent part of a television signal generating device and performs addition processing between identical bits of binary data while only one data has a sign. CONSTITUTION: The digital adding circuit which adds binary multi-bit data A1 to A8 and binary data B1 to B8 consisting of the same number of bits with the binary data while having signs as their most significant digit bits is equipped with adders 1a to 1h which output addition data S1 to S8, an adder which outputs addition data S9 and carry data with binary data B8 of the most significant digit bit showing the sign and carry data of the adder 1h for the most significant digit bit, an exclusive OR circuit 2a, an exclusive OR circuit 2b which outputs binary data S10, and plural arithmetic circuits 3a to 3h which outputs data-clipped binary data N1 to N8 by performing specific arithmetic processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used, for example, as a component of a television signal generator, only one of which is data with a sign, and the addition processing of binary data of the same bit. It relates to a digital adder circuit for performing. In the digital adder circuit in the above television signal generator, so-called data clipping may be performed to fix the upper limit and addition / subtraction of the data in order to make the data of the addition processing result a predetermined bit.

It is desired that such a data clip be realized with a simple circuit structure in order to cope with the downsizing of ICs and the like.

[0003]

2. Description of the Related Art FIG. 5 is a diagram for explaining a conventional digital adder circuit. In the conventional example shown in FIG. 5, 8-bit binary data is subjected to addition processing, and the normal binary data A1 to A8 and the signed binary data B1 to B1.
It has a plurality of adders 11 for performing addition processing of 8 and 8 respectively.

The adder 11 has data A1 to A8 and B1 to
Eight adders 11a to 11a that perform addition processing corresponding to B8
1h, an adder 11i for processing the data A8, B8 and the carry data by the adder 11h. The adders 11a to 11h output the output data S1 after addition.
.About.S8, and carry data input to the respective higher-order adders are output. Further, the adder 11i outputs addition data S9 and code data CO.

FIG. 6 shows an example of input data and output data after addition of the conventional digital adder circuit shown in FIG. First, as one of the input data A1 to A8, “11010
"010" (210 in decimal) is input to the adders 11a to 11i as "01100011" (+99 in decimal because the most significant data is code data) as the other input data B1 to B8.

As a result, the output data S1 to S9 are "1".
0011010 ”(decimal number 309), and the code data CO is“ 0 ”indicating a plus although not shown.

[0007]

According to the conventional digital adder circuit, when "11010010" and "01100011" are added as described above, the result is 10-bit data "0100110101". . Although not shown, the data B with a code
Depending on 1 to B8, the output data may be negative.

As described above, in the digital adder circuit shown in FIG. 5, the addition result data cannot be 8 bits. By the way, when a color signal or a luminance signal is input and processed in a television signal generator or the like, in order to prevent the image from becoming an abnormal color or brightness, the data of the addition processing is It is necessary to put it in.
As this processing, the upper limit and the adjustment of the data are fixed,
So-called data clipping must be done.

As a method of performing data clipping in a digital adder circuit, it can be considered to provide a comparison circuit at the output section of the adder circuit shown in FIG. This is, for example, 8
If it is fixed to bits, the addition result is the maximum number of 8 bits "11111111" (255 in decimal)
If the number exceeds, the data will be clipped to the maximum number,
In the case of negative output data, the minimum number "0"
The data is clipped to "0000000".

That is, the comparison circuit outputs the output data and 1
Compared with "256" and "-1" in the decimal number, "2"
It is necessary to perform data clipping to "255" in the case of 56 "or more, and to" 0 "in the case of" -1 "or less.
However, the circuit for realizing such an operation has an extremely complicated configuration, which leads to an increase in the size of the IC.

It is an object of the present invention to solve the above problems and realize a reliable data clip with a digital adder circuit having a simple structure.

[0012]

According to the present invention for solving the above problems, a plurality of bits of binary data A1 to A8 and the same number of bits as the binary data A1 to A8 and the most significant bit indicate a code. In the digital adder circuit for adding the binary data B1 to B8, the pair of binary data A1 and B
1 is added bit by bit, the carry data is added to the upper bits, and the adders 1a to 1h which output the added data S1 to S8 and the most significant bit 2 indicating the sign are added.
The binary data B8 and the carry data of the adder 1h corresponding to the low level and the most significant bit are input to add data S
9 and the carry data, an exclusive OR circuit 2 for inputting the adder 1i, the binary data B8 of the most significant bit indicating the sign, and the low level and outputting the binary data S9.
a, an output signal of the exclusive OR circuit 2a, and the carry data of the adder 1i, and an exclusive OR circuit 2b for outputting binary data S10; and an adder corresponding to each bit. The addition data S1 to S8 of 1a to 1h are input, respectively, and the addition data S9 of the adder 1i and the output data S10 of the exclusive OR circuit 2b are commonly input to perform predetermined arithmetic processing. It is characterized in that it is provided with a plurality of arithmetic circuits 3a to 3h which output binary data N1 to N8 which are data clipped.

[0013]

According to the digital adder circuit of the present invention, the output data S1 to S8 from each of the adders 1a to 1h, the output data S9 from the adder 1i in common, and the exclusive OR circuit 2b in common also. When the addition result exceeds the maximum number of the predetermined bits by inputting the 3 data of the output data S10 from 3 to 3h to the arithmetic circuits 3a to 3h,
The output data N1 to N8 are all "1", and when the addition result is a negative value, the output data N1 to N8 are all "0".

As described above, according to the present invention, it is possible to reliably perform data clipping without requiring a complicated comparison circuit or the like.

[0015]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram for explaining a digital adder circuit according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of a television signal generator in which the digital adder circuit according to the present embodiment is used.

First, the configuration of the television signal generator will be described with reference to FIG. The television signal generator is for generating a signal called a composite signal necessary for displaying a television image. As shown in FIG. 2, the synchronizing signal generator circuit 10, the digital video encoder 20, and the digital adder circuit 30 are connected to each other. It is the main component.

In such a television signal generator,
The sync signal generation circuit 10 receives the reference clock CLK and outputs a sync signal such as a color burst signal. Also,
The digital video encoder 20 inputs the luminance signal Y and the color difference signals RY and BY, and processes these signals to output digital Y and C signals. The digital adder circuit of the present invention outputs the composite signal COMP for displaying a television image by inputting the output signals Y and C of the digital video encoder 20 and performing addition processing.

The composite signal COMP determines the brightness and hue of the television image. In order to prevent abnormal brightness and hue, if the input data is 8 bits, the output is also set to 8 bits. Need to be fixed. As shown in FIG. 1, the digital adder circuit in the present embodiment has 8-bit binary data A1 to A8 and B1.
B8 (data B8 is coded data) is subjected to addition processing.

This digital adder circuit is provided with eight adders 1a to 1h for respectively inputting the data A1 ..., B1 ... For each bit, and inputs the carry data to the upper bits and adds data S1 to S8. Is being output. Also, the carry data and code data B8 of the adder 1h of the most significant bit, the adder 1i which inputs the signal of the ground (“0”) level and outputs the data S9, and the code data B8 and the ground similarly to the adder 1i. An exclusive OR circuit 2a (hereinafter referred to as an E-OR circuit) to which a (“0”) level signal is input, and further carry data of the adder 1i and EO
It is provided with an E-OR circuit 2b which inputs the output data of the R circuit 2a and outputs the data S10.

Then, these adders 1a to 1i and E-O
The output data S1 to S10 from the R circuit 2b are input to the arithmetic circuits 3a to 3h that perform the arithmetic necessary for data clipping, and are output as 8-bit composite signals N1 to N8. The arithmetic circuits 3a to 3h are for inputting the data S1 to S10 as described above. Specifically, the output data S1 to S8 of the adders 1a to 1h are individually input and the adder 1i is also input. Output data S9 and E
The output data S10 of the OR circuit 2b is commonly input.

Since the synchronizing signal from the synchronizing signal generating circuit 10 shown in FIG. 2 is not directly related to the present invention, it is omitted in the digital adding circuit shown in FIG. FIG.
Is a logic circuit for explaining a specific configuration of the arithmetic circuit 3. Since the plurality of arithmetic circuits 3 have the same configuration, FIG. 3 shows the arithmetic circuit 3a for the first bit as a representative.

The arithmetic circuit 3a includes an inverter 4 for receiving the output data S1 from the adder 1a, an inverter 6 for receiving the output data S10 from the E-OR circuit 2b, and an output signal of the inverter 4 and the E-OR circuit 2b. Output data S1
2-input NOR circuit 5 for inputting 0, 2-input A for inputting the output signal of the inverter 6 and the output data S9 of the adder 1i
It is composed of an ND circuit 7 and a 2-input OR circuit 8 which inputs the output signals of the 2-input NOR circuit 5 and the 2-input AND circuit 7 and outputs a composite signal N1.

FIG. 4 shows an example of input data and output data in the digital adder circuit of this embodiment.
The operation of the digital adder circuit will be described below based on this data example. Data "1" in binary number is "H"
Signal of "high" level, data "0" is "L" (low)
This will be described as a level signal.

As shown in FIG. 4, input data A1 to A8
Is "11010010" (210 in decimal) and the input data B1 to B8 is "01100011" (+99 in decimal because the highest order data is code data), the additions of the adders 1a to 1i in FIG. The result is "10
0110101 ”(decimal number 309). Further, since the data B8 and the signal of the ground level, that is, the signals of "L" and "L" are input to the E-OR circuit 2a,
The output is at "L" level, and the E-OR circuit 2b has
Since "L" and "L" are input, the output S10 thereof is also at "L" level although not shown in FIG.

Therefore, in the case of the arithmetic circuit 3a shown in FIG.
The input signal S1 becomes "H" level, S10 becomes "L" level, and S9 becomes "H" level. In response to this, the output of the 2-input NOR circuit 5 becomes "H" level, the output of the 2-input AND circuit 7 becomes "H" level, and the output signal N1 of the 2-input OR circuit 8 becomes "H" level. Signals S10 and S9
Is fixed at "L" and "H" and is commonly input, the output of the 2-input AND circuit 7 becomes "H" level in any arithmetic circuit, and the output of the 2-input OR circuit 8 Becomes "H" level.

Therefore, the composite signals N1 to N8 are
The maximum number of eight bits is “11111111” (255 in decimal). On the contrary, when the input data B8 is "1" indicating a negative value and the addition result also has a negative value, S10 is always "1", so that the output signal of the arithmetic circuit 3, that is, the composite signal is " 00000000 "
Becomes

As described above, according to the present embodiment, when the output data S1 to S10 from the adder exceeds the maximum number of 8 bits, the arithmetic circuit 3 fixes the maximum number of 8 bits. If the addition result is a negative value, it is fixed to 0 which is the minimum natural number.

[0028]

In the digital adder circuit according to the present invention described above, it is possible to reliably clip data to a specific number of bits with a simple arithmetic circuit without the need for a comparator circuit whose circuit configuration is extremely complicated. Therefore, miniaturization of the IC including the digital adder circuit can be realized.

[Brief description of drawings]

FIG. 1 is a diagram for explaining one embodiment of a digital adder circuit of the present invention.

FIG. 2 is a diagram for explaining a television signal generator using the digital adder circuit of the present invention.

FIG. 3 is a diagram for explaining a specific example of an arithmetic circuit forming a part of the digital adder circuit of the present invention.

FIG. 4 is a diagram showing an example of input and output data in the digital adder circuit of the present invention.

FIG. 5 is a diagram for explaining a conventional digital adder circuit.

FIG. 6 is a diagram showing an example of input and output data in a conventional digital adder circuit.

Claims (3)

[Claims] 1. A plurality of bits of binary data (A1 to A8)
And the binary data (A1 to A8) and the binary data (B1 to B8) having the same number of bits and the most significant bit having a sign, the digital addition circuit including the pair of binary data (A1, B1) is added bit by bit, the carry data is added to the upper bits, and the added data (S1 to S8) is output.
1h), the most significant bit binary data (B8) indicating the code,
Input the carry data of the adder (1h) corresponding to the low (0) level and the most significant bit, and add (S)
9) and the adder (1i) for outputting the carry data, the binary data (B8) of the most significant bit indicating the sign, and the low (0) level are input and the binary data (S9) is output. The exclusive OR circuit (2a), the output signal of the exclusive OR circuit (2a), and the carry data of the adder (1i) are input to input binary data (S1).
0) and an exclusive OR circuit (2b), and addition data (S1 to S8) of the adders (1a to 1h) corresponding to the bits, respectively, and addition of the adder (1i). The data (S9) and the output data (S10) of the exclusive OR circuit (2b) are commonly input, and a predetermined arithmetic process is performed to perform data clipping.
A plurality of arithmetic circuits (3 that output binary data (N1 to N8))
a to 3h). 2. The plurality of arithmetic circuits (3a-3h),
Output data (S1 to S) from the adders (1a to 1h)
8) and the output data (S1) from the exclusive OR circuit (2b).
0) as an input, and a 2-input NO that inputs the output signal of the inverter (4) and the output data (S10) of the exclusive OR circuit (2b).
R circuit (5), output signal of the inverter (6) and the adder (1i)
2-input AND circuit (7) for inputting the output data (S9) of the above, the 2-input NOR circuit (5) and 2-input AND circuit (7)
Input the output signal of the composite signal (N1 to N8)
2. The digital adder circuit according to claim 1, comprising a 2-input OR circuit (8) for outputting 3. A pair of data (A1 to A8, B1 to B8) input to the adders (1a to 1h) is a digital video encoder (20) in a television signal generator.
2. The digital adder circuit according to claim 1, wherein the digital adder circuit is a digital Y signal and a digital C signal which are output signals of the digital adder circuit.