JPH02101824A - Cyclic redundancy inspection code generator - Google Patents

Abstract

PURPOSE:To generate a cyclic redundancy code from a parallel data with simple constitution and to attain high speed processing by outputting the cyclic redundancy check code from an arithmetic circuit as a parallel data when the processing of a data block generating the cyclic redundancy check code is finished. CONSTITUTION:Parallel data D0-D7 latched in a shift register 1 are sequentially inputted to a cyclic redundancy check code (CRC code)arithmetic circuit 4 and the arithmetic operation based on a predetermined generation polynomial is applied. Results of operation C0-C7 are latched in an FF circuit 3 and the circuit 5 supplies a data for each bit to the circuit 4 during the arithmetic period. When the processing of data block is finished, the CRC code is outputted as parallel data d0-d7 from the circuit 4. Thus, the CRC code is generated by the arithmetic operation circuit with simple constitution and hardware, high speed processing is applied and the load of a CPU is relieved.

Description

[Detailed Description of the Invention] [Summary] A device for generating a cyclic redundancy check code (CRC code), which is a block correction code used to perform error detection and correction for each data block in data transmission. The aim is to obtain a device that generates codes, and includes a shift register that latches parallel data, an arithmetic circuit that receives the shift output from this shift register, and latches the arithmetic results of this arithmetic circuit bit by bit. A flip-flop circuit supplies each bit of data to the arithmetic circuit during the calculation period of the shift output from the shift register, and a flip-flop circuit supplies data for each bit to the arithmetic circuit when the processing of the data block for which a cyclic redundancy check code is to be generated is completed. The cyclic redundancy check code is configured to be output as parallel data.

[Industrial application field]

Cyclic redundancy check code is a block correction code used to detect and correct errors for each data block during data transmission.
check code) (hereinafter referred to as CRC code,
) generation device.

[Conventional technology]

CRC codes are widely used to correct code errors that occur during the transfer of serial data. Conventionally, CRC codes are generated from serial data, and devices that generate CRC codes from parallel data are used. was not known.

[Problem to be solved by the invention]

An object of the present invention is to obtain a device that generates a CRC code from parallel data.

[Means to solve problems]

As shown in FIG. 1, there is a shift register l that latches parallel data, an arithmetic circuit 4 into which the shift output from this shift register is input, and an arithmetic circuit 4 that latches the arithmetic results of this arithmetic circuit 4 bit by bit. When the flip-flop circuit 5 supplies each bit of data to the arithmetic circuit 4 during the calculation period of the shift output from the shift register 1, and the processing of the data block for which the cyclic redundancy check is to be generated is completed. The arithmetic circuit 4 is configured to output the CRC code as parallel data.

[For production]

The parallel data latched in the shift register 1 is sequentially shifted out and input to the arithmetic circuit 4 for calculation. The operation result is latched bit by bit in the flip-flop circuit 5, and the flip-flop circuit 5 supplies data for each bit to the operation circuit 4 during the operation period. When the processing of the data block is completed, the arithmetic circuit 4 outputs the CRC code as parallel data.

〔Example〕

FIG. 1 is a diagram showing the configuration of an embodiment in which the present invention is applied to a CRC code generation device that generates a CRC code for 8-bit parallel data. This will be explained with reference to the time chart.

The hexadecimal counter 2 is used to generate the #2 clocks ck and ck' shown in FIG. Then, when the start signal S shown in FIG. 6(d) synchronized with the fall of the #1 clock CK is applied to the reset terminal of the counter 2, counting of the #1 clock starts from the rise of the start signal S, Same figure (e).

As shown in (f), the #2 clock ck has a count output whose period is twice that of the #1 clock and has opposite phases to each other.

ck' is supplied to the clock terminal of the shift register 1 and the clock terminal of the flip-flop circuit 5.

Then, when this hexadecimal counter 2 counts "15" as shown in the timing [phase]' and [phase] of FIG. 2, the carry C shown in FIG. is supplied to the other terminal of the OR circuit 3 whose one input terminal is supplied with the #1 clock GK.
Even if one clock is input to this counter 2, the output of the OR circuit 3 becomes a carry signal waveform, and this counter stops counting and stops supplying the #2 clocks ck and ck'.

On the other hand, the parallel data input terminal of the shift register 1 is supplied with 8-bit parallel data D (FIG. 2(b)) in which the most significant digit is D7 and the least significant digit is Do.
The timing of the rise of the #2 clock ck' when the mode signal M supplied in synchronization with the fall of the first clock GK is "Oo" and the counter 2 is reset by the start signal S and starts counting anew. Therefore, the parallel data D is latched into this shift register I.

As shown in Figure 2 (hl), the timing of this latch is
The most significant digit D7 bit is output, but this output bit changes Ds and D every time the clock is input in shift mode.
As shown in this figure, the values change sequentially from s...-.

Subsequently, the calculation result in the calculation circuit 4 for calculating a predetermined generator polynomial is calculated for each digit c0 to C1 at the timing indicated by ■, for example, by a D-flip-flop corresponding to each bit. Each bit is written into the flip-flop circuit 5 and latched.

At the next timing ■, the shift register 1
The second digit bit D of the 8-bit parallel data latched in is shifted out and input to the arithmetic circuit 4, and the result of this arithmetic operation is sent to the flip-flop circuit 5 for each bit at the timing of Lunch will be served.

At the timing of ■ by the next #2 clock, the third digit from the high-order bit D is shifted out from the shift register to the arithmetic circuit 4.

An operation is performed together with the data for each digit from the flip-flop circuit that latches the processing result for the Db bit, and the result is latched again for each digit in the flip-flop circuit 5 at the next timing (■). be done.

In this way, when the calculation up to the least significant digit D0 that constitutes the parallel data is completed at the timing of [phase],
A carry is output from the hexadecimal counter 2, and the counting operation of this counter is stopped as described above, and the processing for one parallel data D0 to D7 is completed.

Note that the calculation result in the calculation circuit 4 based on the shift out at the time of [phase] and the output of the flip-flop circuit 5 is as follows.
Start signal S for next 8-bit parallel data
becomes “0” and #2 clock ck' rises [phase]
It is latched at the timing of

Such processing is repeated for each parallel data belonging to the data block for which a CRC code is to be generated, and when the processing of all the parallel data belonging to this data block is completed, the gate 6 is turned on and the output C0 of the arithmetic circuit 4 is
~C6, the required CRC code for this data block becomes parallel data d0~d7.
obtained as.

CRC code calculation circuit 4 in the embodiment shown in FIG.
is an example when x"+x'+x'+x" +1 is used as the generating polynomial, and the FOR circuit 41.4z+4
The above polynomial is calculated by hardware including z and 4a, but since this type of generating polynomial and its calculation circuit are well known, a detailed explanation of its operation will be omitted.

FIG. 3 shows a configuration diagram of a data processing device to which the CRC code generation device of the present invention is applied. The CRC code generation device 10 explained with reference to FIG. The CPU is connected to the memory 15 by the control bus 13, address bus 14, and data bus 12.
It is connected to the.

The CRC code generator 10 generates a CRC code before processing the first parallel data of the data block.
It is reset by a reset signal from UII, and this CPU takes out data one byte at a time from the buffer area of memory 15 and stores this CRC as parallel data.
The signal is supplied to the shift register (FIG. 1) of the code generation device 10.

Further, this CPU generates the mode signal shown in FIG. 2(C) and the start signal shown in FIG. Generate a code.

When the processing of the data block for which the CRC code is to be generated is completed, the CPU II applies a gate signal to the CRC code generator to turn on the gate 6 shown in FIG. The CRC code on this data bus is added to the end of the data block and transmitted to the receiving side.

It goes without saying that the receiving side uses this CRC code to detect and correct errors in received data.

In the above explanation, 8-bit parallel data was used as an example, but in the case of 16-bit parallel data, the hexadecimal counter 2 in FIG. It is obvious that each of the elements 5 may be constructed of 16 elements.

Further, it goes without saying that the arithmetic circuit 4 at this time must be able to perform the required generator polynomial arithmetic on hexadecimal data.

Similarly, CR for parallel data of 16 bits or more
Needless to say, it is also possible to configure a C code generation device.

The special effect of reducing the burden on the CPU can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a time chart for explaining its operation, and FIG. 3 is a block diagram of a data processing apparatus to which the CRC code generation apparatus according to the present invention is applied. 1...Shift register, 4...Arithmetic circuit, 5...
Flip-flop circuit, 6... gate circuit. 〔Effect of the invention〕

Claims (1)

[Claims] A shift register (1) that latches parallel data, an arithmetic circuit (4) into which the shift output from the shift register is input, and latches the arithmetic results of the arithmetic circuit (4) bit by bit. At the same time, during the calculation period of the shift output from the shift register, each bit of data is sent to the calculation circuit (
4), and outputs the cyclic redundancy check code as parallel data from the arithmetic circuit (4) when the processing of the data block for which the cyclic redundancy check code is to be generated is completed. A cyclic redundancy check code generation device characterized by: