JP2848734B2 - Error detection and correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detecting / correcting apparatus for performing error correction on an information bit string of received data.

[0002]

2. Description of the Related Art Conventionally, as an error detection / correction method, a transmission side obtains a check bit sequence for a transmission information bit sequence using a generator polynomial, transmits a transmission bit sequence including the transmission information bit sequence and the check bit sequence to a reception side, and performs reception. On the side, there is a method in which a received bit string (equal to a transmitted bit string if there is no error) is divided by the above-described generator polynomial, and the division result is used as an address to search a memory table to obtain and correct error bit information.

[0003] This conventional system will be generally described with reference to FIG. Here, a (n−1) -order remainder for an m-bit information sequence is given as a check bit sequence using an n-th generation polynomial, and only one-bit errors are corrected. In the following description, the expression “bit string” also means a code polynomial using the bit string as a coefficient in some cases.

[0004] In FIG. 2, the remainder operation unit 1 on the transmission side includes a generator polynomial G (X) and a transmission information bit sequence D
From (X), the check bit string E satisfying the following equation (1) is obtained.
(X). O (X) = X ⁿ · D (X) + E (X) = G (X) · Q (X) (1) That is, the information bit string D (X) is generated by the polynomial G (X)
To obtain a remainder bit string E (X).

[0005] The multiplexing section 2 receives a bit string X ⁿ · D (X) + E (X) obtained by adding the check bit string E (X) to the lower side of the transmission information bit string D (X) as a transmission bit string O (X). Send to the side. As shown in equation (1), this transmission bit string O (X) is divisible by the generator polynomial G (X). Q (X) in equation (1) is the transmission bit string O
The quotient obtained by dividing (X) by the generator polynomial G (X).

An error may enter the transmission bit string O (X) through transmission. Here, the error information is
(X), the bit string I (X) received on the receiving side
Is represented by equation (2). I (X) = O (X) + ER (X) = G (X) · Q (X) + ER (X) (2) Here, if there is no error, the received bit string I (X)
Is equal to the transmission bit string O (X), the generator polynomial G
Divide by (X). On the other hand, if there is an error, it cannot be divided by the generator polynomial G (X), and a remainder bit string R (X) is generated. That is, a remainder bit string R (X) that satisfies Expression (3) is generated. I (X) = G (X) · Q ′ (X) + R (X) (3) where Q ′ (X) is a quotient. G (X) in equation (2)
In Q (X) + ER (X), since the first term is divisible by the generator polynomial G (X), the remainder bit string R (X) is the remainder bit string obtained by dividing the error information ER (X) by the generator polynomial G (X). And the remainder bit string R (X) is a bit string reflecting the error information ER (X). That is, the bit string reflects the number of error bits and the position of the error bit.

[0007] Then, on the receiving side, the residual bit string R
A memory table 4 in which (X) is associated with an error pattern such as an error bit position is provided, and the remainder operation unit 3 divides the received bit string I (X) by a generator polynomial G (X) to obtain a remainder. The memory table 4 is searched by the bit string R (X) to derive the presence or absence of an error or an error bit position in a certain case. If error correction is possible, the correction bit string C (X) is given to the error correction circuit 5. , Received bit string I
The error bit of (X) is corrected.

FIG. 3 shows an example of a conventional specific configuration of an error correction circuit 10 (corresponding to the circuit 5 in FIG. 2) which implements 8-bit parallel processing. This configuration example employs an eighth-order generator polynomial X ⁸ + X ² + X + 1, and adds a seventh-order check bit sequence (therefore, the number of bits is 8) to a 32-bit information bit sequence to form a transmission bit sequence. It is an example. In this example, the received bit string is 40 bits, but the error correction circuit 10
Is input to

[0009] Such a system is adopted as an error detection / correction system in asynchronous transfer mode (ATM) communication.

Referring to FIG. 3, the error correction circuit 10 includes, as described above, a received bit string S of 8 bits each.
(X) and the memory table 11 (corresponding to Table 4 in FIG. 2) output 40 according to the remainder bit string R (X).
The bit correction bit sequence C (X) is input.

The error correction circuit 10 includes a memory table 11
Latches the correction bit string C (X) output from
Bit flip-flop circuit 12, five 8-bit flip-flop circuits 13 to 17 for latching an 8-bit received bit string S (X), and five 8-bit exclusive ORs for correcting predetermined bits. Circuits 18-22
It is composed of Five flip-flop circuits 1
3 to 17 and 5 exclusive OR circuits 18 to 2
2 are provided alternately and cascaded with the flip-flop circuit 13 at the head of the receiving side, and the 8 bits latched in each of the flip-flop circuits 13,... ., 22 are input to one of the input terminals. Each exclusive OR circuit 18,
, 22 are connected to the 40-bit correction bit string C (X) latched by the flip-flop circuit 12.
8 bits C (0) to C (7) related to self,
.., C32) to C (39) are input.

FIG. 4 shows the input timing of the received bit string S (X) and the remainder bit string R (X). 1
The remainder bit string R is synchronized with the last (fifth) received bit string S (X) constituting the block data (40 bits).
(X) is input. Therefore, the corrected bit string C (X) is output from the memory table 11 in synchronization with the last (fifth) received bit string S (X). That is, each flip-flop circuit 13,...
) When the data of 8 bits each constituting the bit) is latched, the flip-flop circuit 12
(X) is latched, and an exclusive OR process is performed.

Here, in the correction bit string C (X), the bit at the correction position is “1” and the other bits are “0”. Exclusive OR processing is to invert the other input when one input is "1" and output it, and to output the other input as it is when one input is "0". Exclusive or circuit 18, ..., 2
The error bit in the received bit string S (X) is corrected by the process of 2.

[0014]

However, the conventional error detection / correction device has a problem that the memory size is very large. In the case of the example of FIG. 3 described above,
An 8-bit remainder bit string R (X) is stored in the memory table 11.
Because Type outputs a 40-bit error correction bit string C (X), and be required to the memory table 11 and 2 ⁸ words × 40 bits configuration, the memory scale was very large.

In addition, since the memory size is large, it is difficult to access the memory at high speed, and it is difficult to apply to high-speed processing. Since the example of FIG. 3 is applied to high-speed processing ATM communication, the problem that it is not suitable for high-speed processing is very large.

The present invention has been made in view of the above points, and can reduce the size of a memory table for outputting an error correction bit string, and can perform error correction processing at high speed. It is intended to provide a device.

[0017]

In order to solve the above-mentioned problem, according to the present invention, an m-bit information bit string is represented by n bits.
An error pattern provided on the receiving side to which a bit string of m + n bits given to the information bit string as a check bit string is a remainder obtained by dividing the remainder by the following generator polynomial (m is an integral multiple of n) In the error detection / correction device which has a reference memory table and which can correct an error of only one bit in the received bit string by its output, a memory table which outputs an n-bit corrected bit string is applied as the memory table, A first remainder calculating means for outputting a first remainder bit string obtained by dividing a s (s is 1 to (m + n) / n-
A second remainder operation means for obtaining a remainder obtained by dividing a polynomial obtained by multiplying the remainder bit sequence of X) by X ⁿ by a generator polynomial as an s + 1th remainder bit sequence is provided. And the t-th (t is 1 to
By using the corrected bit string output from the memory table with the remainder bit string of (m + n) / n as an address,
An error correction process is performed on the t-th n bits obtained by dividing the received bit string into n bits, and an error of only one bit in the received bit string is corrected.

[0018]

In the present invention, the received bit string is m + n bits in order to reduce the capacity of the memory table and shorten the delay time caused by processing the memory table.
A memory table that outputs an n-bit corrected bit string is used as the memory table. That is, the received bit string is divided into n bits, and error correction processing is performed on each n bits to correct an error of only one bit in the received bit string.

A first division of the received bit string into n bits
If there is only one bit error in the nth bit,
Based on the first remainder bit string obtained by dividing the entire received bit string by the generator polynomial by the first remainder calculation means, the first remainder calculation means corrects the data according to the correction bit string output from the memory table. Second
If there is only one bit error in the nth bit,
Based on the second remainder bit string obtained by dividing the polynomial in which the first remainder bit string is multiplied by X ⁿ by the generator polynomial, the second remainder operation means corrects the data according to the correction bit string output by the memory table. Hereinafter, a one-bit error is similarly corrected.

When there is only one bit error in the received bit string, the error naturally exists only in any one of n bits obtained by dividing the received bit string into n bits. In consideration of this, an examination by an equation shows that, as described above, when there is a 1-bit error only in the t-th n bits, the second remainder calculating means sets the t-1 It has been found that the correction can be made in accordance with the correction bit string output from the memory table, based on the t-th remainder bit string obtained by dividing the polynomial obtained by multiplying the bit string by X ⁿ by the generator polynomial.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. This embodiment is provided on the receiving side that receives the transmission bit string O (X) transmitted from the transmitting side in FIG. That is, an n-th order generator polynomial G
Using (X), a transmission bit string O (X) is given, in which the (n-1) -order remainder of the m-bit information bit string D (X) is added to the information bit string D (X) as a check bit string E (X). It is provided on the receiving side, and enables correction of only one bit error. In this embodiment, m is an integral multiple of n.

FIG. 1 shows the configuration of an error detection / correction device on the receiving side of this embodiment. Also in this embodiment, a memory table 32 in which a residual bit string R (X) is associated with an error pattern such as an error bit position is provided in advance.
(X) is output to the error correction circuit 33 to correct the error bit of the received bit string I (X).

However, in this embodiment, m + n
Instead of outputting and correcting a correction bit string for the entire reception bit string I (X), the reception bit string I (X)
The error correction is executed by outputting a correction bit string for each n-bit unit obtained by dividing (X) into n bits. Therefore, the memory table 32
And its access configuration is different from the conventional one. That is, the memory table 32 stores, for one address, n in the received bit string I (X) of m + n bits.
It is configured to output a correction bit string for bits. The address for the memory table 32 is generated by the first remainder operation unit 30 or the second remainder operation unit 31.

The first remainder operation unit 30 has the above (2)
The received bit string I (X) represented by the equation is input, and the first remainder operation unit 30 satisfies the above equation (3) obtained by dividing the received bit string I (X) by the generator polynomial G (X). The remainder bit string R (X) (hereinafter, this remainder bit string is represented by R1 (X)
). The remainder bit string R1 (X) is provided to the second remainder operation unit 31 and the memory table 32. When receiving the remainder bit string R1 (X) from the first remainder operation unit 30, the memory table 32 determines whether or not there is an error bit in the reception bit string I (X) and determines whether a one-bit error occurs in the reception bit string I (X). ) Is determined in the upper n bits, and a 1-bit error is detected in the received bit string I.
When it is in the upper n bits of (X), a correction bit string C (X) consisting of n bits is given to the error correction circuit 33 and corrected.

As described above, in the memory table 32, 1
Information that can be used to determine whether or not a bit error is present in the upper n bits of the received bit string I (X), and a case where a 1-bit error is present in the upper n bits of the received bit string I (X) The correction bit string C (X) is stored in an area using the remainder bit string R1 (X) as an address.

When the 1-bit error is not present in the upper n bits of the received bit string I (X), the second remainder operation unit 31 calculates the remainder bit string R2 (X )
Is calculated and given to the memory table 32 and its own remainder bit string input terminal. X ⁿ · R 1 (X) = G (X) · Q 2 (X) + R 2 (X) (4) where Q 2 (X) is X ⁿ · R 1 (X) generating polynomial G
The quotient divided by (X).

When the remainder bit sequence R 2 (X) is given from the second remainder operation unit 31, the memory table 32 determines that a 1-bit error has occurred in n bits of the upper n + 1st to 2nth bits of the received bit sequence I (X). Judge whether it is inside or not,
When a 1-bit error is present in the n bits, a correction bit sequence C (X) consisting of n bits is given to the error correction circuit 33 to be corrected.

Hereinafter, a one-bit error occurs when the received bit string I
Information that can determine whether or not it is in the upper n bits of (X), a corrected bit string C (X) when a 1-bit error is in the upper n bits of the received bit string I (X), etc. Is stored in the memory table 32 in which a one-bit error is detected from the upper n + 1-th of the received bit string I (X).
It demonstrates that error correction can be performed when it is within n bits up to n.

As described above, the received bit string I (X)
Is obtained by adding error information ER (X) to the transmission bit string O (X), and the transmission bit string O (X) is obtained by the generator polynomial G (X).
The remainder bit string R1 obtained by dividing (X) by the generator polynomial G (X)
(X) is equal to the remainder bit string obtained by dividing the error information ER (X) by the generator polynomial G (X). That is, the following equation (5) holds. ER (X) = G (X) · Q1 (X) + R1 (X) (5) Here, the error information ER (X) is expressed as p (= ( Considering m + n) / n) parts ER1 (X), ER2 (X),..., ERp (X). ER (X) = ER1 (X) + ER2 (X) +... + ERp (X) (6) If there is an error of only one bit, only one of the parts takes a value other than 0, and The part is zero. 1
If there is no bit-only error in the upper n bits,
ER1 (X) is 0. Therefore, X ^{n is} added to ER (X).
Can be considered as a bit string of the same order as the original error information ER (X), as shown in equation (7). ^Xn・ ER (X) = ^Xn・ ER2 (X) + ^Xn・ ER3 (X) +... + ^Xn・ ERp (X) (7) In the memory table 32, error information ER (X) is generated by a polynomial G The error information ER is obtained based on the remainder bit string R1 (X) divided by (X) (actually, the received bit string I (X) is obtained as the remainder divided by the generator polynomial G (X)).
Information that can correct a 1-bit error in the upper n bits of (X) is stored. Therefore, the error information ER
Polynomial X ⁿ · ER (X) which can be considered in the same way as (X)
Divided by a generator polynomial G (X)
Is obtained, information that can correct a 1-bit error in the upper n bits of the polynomial X ⁿ ER (X) of m + n bits can be extracted from the information in the memory table 32. The upper n bits of the polynomial X ⁿ · ER (X) are the n + 1 to 2n n bits of the error information ER (X).
Therefore, the information extracted from the memory table 32 based on the remainder bit string R2 (X) is the error information ER (X), and thus the upper n + 1 of the received bit string I (X).
It becomes a correction bit string for n bits from the 2nd to the 2nth.

Since the error information ER (X) is unknown, the remainder bit string R2 (X) cannot be obtained by dividing the polynomial X ⁿ · ER (X) by the generator polynomial G (X). Therefore, it is considered that the remainder bit string R2 (X) is obtained from known information. The polynomial X ⁿ · ER (X) is given by (5)
From the equation, it can be seen that it is represented by the following equation (8). ^Xn・ ER (X) = ^Xn・ G (X) ・ Q1 (X) + ^Xn・ R1 (X) (8) Since the first term on the right side is divisible by the generator polynomial G (X), the remainder bit string R2 (X) is the second term X on the right side of equation (8).
^It is equal to the remainder of ⁿ · R1 (X) divided by the generator polynomial G (X). That is, the remainder bit string R2 (X) obtained by dividing the polynomial X ⁿ · ER (X) by the generator polynomial G (X) is described above.
As shown in equation (4), it is equal to the remainder bit string R2 (X) obtained by dividing the polynomial ^Xn · R1 (X) by the generator polynomial G (X).

As described above, the second remainder operation unit 31 obtains the remainder bit string R2 (X) satisfying the above equation (4), that is, multiplies the remainder bit string R 1 (X) by X ⁿ . A remainder bit string R2 (X) obtained by dividing the polynomial X ⁿ · R 1 (X) by the generator polynomial G (X) is obtained in the memory table 32.
, The upper n bits of the received bit string I (X)
It is possible to determine from the memory table 32 a correction bit string C (X) that can determine whether or not there is only one bit error in only n bits from the + 1st to 2nth bits, and correct it if there is. Can be.

If there are no error bits up to the upper 2n-th bit of the received bit string I (X), similar to the above,
The second remainder operation unit 31 obtains a new remainder bit string R3 (X) by referring to the memory table 32 according to the following equation (9), thereby obtaining the upper 2n + of the received bit string I (X).
It is possible to determine from the memory table 32 a corrected bit string C (X) that can determine whether or not there is an error of only one bit only in the n bits from the first to the 3nth, and correct the error if there is. Can be. X ⁿ · R 2 (X) = G (X) · Q 2 (X) + R 3 (X) (9) The second remainder operation unit 31 performs the same processing as described below.

Therefore, according to the above-described embodiment, it is possible to detect and correct an error using the memory table 32 having a much smaller capacity than the conventional one. As a result, it is suitable for high-speed processing.

Next, a description will be given of a second embodiment of the present invention in which 8-bit parallel processing is performed. FIG. 5 shows a specific configuration example of this embodiment. This embodiment uses 8
Using the following generator polynomial X ⁸ + X ² + X + 1, a transmission bit sequence (reception bit sequence) obtained by adding a 7th-order check bit sequence (therefore, the number of bits is 8) to a 32-bit information bit sequence
Is given. As mentioned above, this is the AT
This is used in M communication.

In FIG. 5, the error detection / correction device 4
0 is the memory table 41 for outputting the 8-bit error bit string C (X) and the 8-bit received bit string S1
(X) to S5 (X) latch flip-flop circuit 4
2 to 46 and a flip-flop circuit 47 for latching the error bit string C (X) output from the memory table 41.
And an 8-bit exclusive OR circuit 4 for error correction
8, a first remainder operation unit (not shown), and a second remainder operation unit 49.

At the correction timing of the first received bit string S 1 (X), the second remainder operation section 49 gives the remainder bit string R 1 (X) given from the first remainder operation section to the memory table 41 as it is. , J-th (j is 2 to 5)
In the correction timing of the received bit string Sj (X), (10)
The remainder bit string Rj (X) satisfying the expression is directly provided to the memory table 41. X ⁸ · R j -1 (X) = G (X) · Q j (X) + R j (X) (10) The memory table 41 stores the given remainder bit string Ri
When (X) (i is 1 to 5) is 0, a corrected bit string C (X) of a 0-bit string is output, and the given remainder bit string R
If i (X) is other than 0 and there is only one bit error in the currently targeted 8-bit received bit sequence Si (X), a correction bit sequence C (X) for correcting the error is output, and the remainder bit sequence Ri ( If X) is other than 0 and it is detected that there are two or more error bits in the received bit string I (X), a detected bit string is output. The correction bit string C (X) of at least 0 and the correction bit string C (X) for 1-bit correction are latched by the flip-flop circuit 47 and applied to one input terminal of the exclusive OR circuit 48.

The above-mentioned five flip-flop circuits 42
46 and the exclusive OR circuit 48 are cascaded in this order, and the flip-flop circuit 46 at the final stage is connected.
Is input to the other input terminal of the exclusive OR circuit 48. The exclusive OR circuit 48 includes the flip-flop circuit 4
8 output from the memory table 11 latched in 7
Based on the corrected bit sequence C (X), the received bit sequence S latched by the flip-flop circuit 46 at the last stage
If there is an error bit in (X), it is corrected.

FIG. 6 shows a timing chart of each part of the second embodiment, in which only one bit in the third 8-bit received bit string S3 (X) has an error.

As shown in FIG. 6, the whole received bit sequence I
The remainder bit string R1 (X) obtained from (X) is the last (5
5) is input to the configuration shown in FIG. 5 in synchronization with the 8-bit received bit string S5 (X). In this example, since there is a one-bit error, the remainder bit string R1 (X) is not 0, and the second remainder operation unit 49 sets the remainder bit string R1
After passing through (X), the remainder bit strings R2 (X), R3 (X), R4 taking values other than 0 obtained according to equation (10)
(X) and R5 (X) are sequentially output. Since there is only one bit error in the third 8-bit received bit string S3 (X), the memory table 41 stores the remainder bit string R3
Correction bit string C other than 0 only when (X) is given
(X) is output and latched by the flip-flop circuit 47. At this latch timing, the third 8-bit received bit string S3 (X) is latched in the flip-flop circuit 46 at the last stage. Thus, the erroneous bits are corrected by the exclusive OR circuit 48.

[0040] Thus, this embodiment also, it is possible to error detection and correction using memory table 41 of the conventionally remarkably small volume (2 ⁸ words × 8 bits), moreover, an error which is suitable for high-speed processing A detection / correction device can be realized.

It should be noted that the present invention can be applied to both error detection and correction devices for parallel processing and serial processing. Further, the remainder operation unit and the like may be realized by a hardware configuration or a software configuration.

[0042]

As described above, according to the present invention, a memory table which outputs an n-bit corrected bit string equal to the degree of a generator polynomial is applied, and at the same time, m + n
An error correction process is executed for each n bits obtained by dividing a received bit sequence of bits into n bits, so that an error of only one bit in the received bit sequence is corrected, so that the memory capacity can be reduced and suitable for high-speed processing. Error detection
A correction device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment.

FIG. 2 is a block diagram showing a conventional error detection / correction method.

FIG. 3 is a block diagram showing a main configuration of a conventional specific error detection / correction device.

FIG. 4 is a timing chart of an input signal to the device of FIG. 3;

FIG. 5 is a block diagram showing a second embodiment.

FIG. 6 is a timing chart of each part of the second embodiment.

[Explanation of symbols]

30: first remainder operation unit, 31: second remainder operation unit, 3
2 ... memory table, 33 ... error correction circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-28133 (JP, A) JP-A-63-79142 (JP, A) JP-A-61-7729 (JP, A)

Claims (1)

(57) [Claims] 1. An m + obtained by dividing a m-bit information bit sequence by a generator polynomial of the order n (where m is an integer multiple of n) and assigning the remainder as a check bit sequence to the information bit sequence
an error detection / correction device provided on a receiving side to which an n-bit bit string is provided, the apparatus including a memory table for referring to an error pattern and capable of correcting an error of only one bit in the received bit string by an output thereof; A memory table that outputs an n-bit corrected bit string is applied as the memory table, and a first remainder calculating unit that outputs a first remainder bit string obtained by dividing the entire received bit string by a generator polynomial; The remainder obtained by dividing a polynomial obtained by multiplying the remainder bit string of (m + n) / n-1) by X ⁿ by a generator polynomial is s +
A second remainder calculating means for obtaining the remainder bit string as a 1-residue bit string. The correction bit string output from the memory table using the t-th (t is 1 to (m + n) / n) remainder bit string as an address is used to convert the received bit string into n T divided into bits
An error detection / correction device, wherein an error correction process is performed on a n-th bit to correct an error of only one bit in a received bit string.