KR950009689B1 - Crc apparatus cepable of dividing block boundary in byte synchronized data - Google Patents

Abstract

an N byte shift register for shifting byte column to be decoded by N byte to output the shifted byte column; a compensation polynomial expression driver for driving a compensation polynomial expression; and a device for performing operation of a subtraction of 2 by a compensation polynomial expression and operation of division of 2 by a generation polynomial module, wherein division of block boundary is made in byte synchronized data.

Description

Circular margin checking device that can distinguish block boundary from byte synchronized data

1 is a block diagram of a circulating margin inspection apparatus that can distinguish the conventional block boundary.

2 is a block diagram of a circulating margin inspection apparatus capable of classifying block boundaries according to the present invention.

3 is an exemplary view when the circulatory margin inspection apparatus capable of distinguishing block boundaries according to the present invention.

* Explanation of symbols for main parts of the drawings

11: CRC operator 12: delay means

13 CRC calculation derivation means 14 coincidence detection means

21: N byte shift register 22: compensated polynomial driver

23: Subtract 2 by Compensation Polynomial Module and Divide by 2 by Polynomial Module

31,54: Exclusive OR gate for subtracting 2 with compensated polynomial modulo

300: 5-byte shift register 310: compensated polynomial driver

319 to 326 D flip flop

330,353 Exclusive OR gate for dividing into two generation polynomial modules

390: 8 input OR gate

According to the present invention, data inputted by a cyclic redundancy check (CRC), which is one of error detection and correction methods using a cyclic code, is byte-synchronized, but the block boundary of the cyclic code is known. The present invention relates to a CRC apparatus capable of distinguishing a block boundary that outputs a block boundary by continuously calculating a byte string containing a cyclic code when it cannot.

In the conventional CRC apparatus, the operation is performed in a state where a boundary is given, so that in order to know the block boundary, each time a byte sequence constituting the block is sequentially changed, that is, a code word constituting the block is directed toward the most significant byte. Whenever a block is moved by one byte and a new least significant byte, there is a problem that the operation of repeating the number of bytes constituting the block is repeatedly performed.

FIG. 1 shows a CRC calculator 11, a delay means 12, a CRC calculation derivation means 13, and a HEC synchronizer in a CRC calculation method and an ATM exchange method of JP-A 4-2824753 as an improved invention. It consists of the detection means 14.

The CRC (circular free space inspection) device that can distinguish the block boundary shown in the drawing can reduce the amount of hardware than the conventional one by avoiding iterative calculation, which is a problem of the conventional CRC device, but this method delays the CRC operation result. Since the result is compared with the result of CRC operation on the new block boundary, the circuit comparing the calculated result is additionally inserted and the result to be calculated is not known until after the least significant byte of the block is output.

Therefore, in order to solve the above problem, the present invention does not operate as much as the number of bytes constituting the block even if the byte strings constituting the block are sequentially changed, and operates only the number of newly added bytes or the number of bytes excluded from the block. It is an object of the present invention to provide a circular margin checking apparatus capable of distinguishing a block boundary from byte-synchronized data that distinguishes a block boundary and outputs an operation result before a block start point.

In order to achieve the above object, the present invention relates to an N-byte shift register means for initializing a mode of N bytes at a logic level '0' and outputting by shifting the byte string to be decoded by N bytes. X ^n-1 , which is the most significant bit of the N byte block code, is divided into two by the module polynomial for each bit (B _s x ^s ) of the byte connected to the byte data output side and output from the N byte shift register means. C (X, B _s ) x = B _s x ^s {a _r-1 x ^r-2 +... … Compensation polynomial driving means for driving a compensation polynomial of + a ₂ x ^r2 + a ₁ x ^r1 + a ₀ } x, the compensation polynomial driving means and a byte data to be decoded connected to the byte data external input terminal. The modulo polynomial of C (x, B ₇ ) x polynomials configured in the compensation polynomial driving means in higher bit order, and then performing the two divisions of the modulus with the generated polynomial G (x). Compensating polynomial driving means for 1 byte in bit units, respectively, after modulo 2 subtraction with C (x, B ₆ ) x polynomial driven by driving means, and then dividing modulo 2 with generating polynomial G (x), respectively. It is characterized in that it comprises a means for subtracting 2 by a compensated polynomial module and generating a divide by 2 polynomial module, which repeatedly executes C (x, B ₀ ) x polynomials driven in and outputs the result when the rest is '0'. Gong.

Next, in order to clearly explain the operation principle of the present invention by mathematical analysis, it will be described in detail by bit operation.

The size of the block is n bits, transmitted as the G (x) generation polynomial, and the n-bit block is T _k (x) at any moment k that does not know the block boundary. When the input bit is a _k and the bit input at the moment K + 1 in the bit string is a _{k + 1} , the n-bit block at the moment K + 1 is T _{k + 1} (x) The block is,

T _k (x) = a _kn-1 x ^n-1 + B _k (x) + a _k

Where a _kn-1 x ^n-1 is the most significant bit of the n-bit block at the moment K and a _kn-1 is the bit entered (n-1 times before the k moment) for kn-1 A _k is the least significant bit of the n-bit block at k instants and the bit input at k instants, and B _k (x) is the remaining bits except the most significant bit and least significant bit in the n bit block at k instants.

Further, the n-bit block at k + 1 instants is

T _{k + 1} (x) = a _k- nx ^n-1 + B _{k + 1} (x) + a _{k + 1}

As are means where a _kn x ^n-1 is a k + a most significant bit of n bit blocks in one moment and a _kn is a bit (bit before n-1 times with respect to k time) entered in the kn moment, and a _{k +1} means the least significant bit of the n-bit block at k + 1 moments and the bit entered at k + 1 moments, except for the most significant bit and least significant bit in the n-bit block at k _{k + 1} (x) k + 1 moments. The remaining bits. The result of dividing n-bit block into modulo polynomial G (x) by modulus at any k moment is {a _kn-1 x ^n-1 + B _k (x) + a _k } / G (x), {a _kn-1 x ^n-1 + B _k (x) + a _k } / G (x) is set to R _x (x), and a _kn-1 x ^n-1 / G (x) is If C _k (x), then the remainder of {B _k (x) + a _k } / G (x) is R _x (x) -C _x (x).

However, since the n-bit block at the moment k + 1 is T _{k + 1} (x) = (B _k (x) + a _k ) x + a _{k + 1} , the n-bit block is generated at the moment K + 1. The result of modulo division by x) is [{B _k (x) + a} x] / G (x) + a _{k + 1} / G (x) and [{B _k (x) + a _k } x] / G (x) is {R _k (x) -C _k (x)} x, so the remainder of T _{k + 1} / G (x) is given by the following formula {R _k (x) -C _k (x)} x + a equals the remainder of _{k + 1} / G (x).

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a CRC device according to the present invention, in which 21 represents an N-byte shift register, 22 represents a compensation polynomial driver, 23 represents two subtractions of a compensation polynomial module, and two divisions of a generation polynomial module.

As shown in the figure, a detailed description of a CRC device capable of distinguishing block boundaries from byte-synchronized data is as follows.

First, the N-byte shift register 21 initially initializes all of the N bytes to a logic level '0', shifts the bytes to be decoded one byte at a time, stores N bytes of bytes, and stores the time K + N. Prints the bytes that were entered at the moment K.

In addition, the compensation polynomial driver 22 is connected to the N-byte shift register 21 so that the bit of the byte output from the N-byte shift register 21 is B _s x ^s (s is an integer of 0 to 7). If B _s is a coefficient with 0 or 1, B ₇ is 0 or 1 with the most significant bit count and B ₀ is 0 or 1 with the least significant bit count, then N bytes of block code for each bit (B _s x ^s ) The most significant bit x ^n-1 is divided into two by the generation polynomial (G (x)), and the rest is shifted in the direction of the upper bit by one bit and then driven.

C (x, B _s ) x = B _s x ^s (a _r-1 x ^r-1 + a _r-2 x ^r-2 +... … + a ₂ x ² + a ₁ x ¹ + a ₀ } x

Therefore, when the byte output from the N byte shift register 21 is '0', C {x, B _s x ^s ) x = o is driven.

Subtracting and generating the polynomial 2 by the compensation polynomial modulo 2 divide 23 is connected to the compensation polynomial driver 22 and is driven by the C (operated by the compensation polynomial driver 22 with respect to the byte string to be decoded at each byte interval. x, B ₇ x ⁷ ) x Subtract modulo 2 in order of higher bits with polynomial and divide by modulo 2 with generated polynomial G (x) to make the remainder higher and the next bit of input byte into lower bit. By subtracting modulo 2 by C (x, B ₆ ) x polynomials again driven by the compensated polynomial driver 22 and then dividing by modulo 2 by the generated polynomial G (x), respectively. 22) sequentially repeats the operation for 1 byte from the driven C (x, B ₀ ) x polynomial, and when the rest is '0', outputs the result to the outside.

FIG. 3 is an example of a CRC device capable of distinguishing block boundaries from byte-synchronized data of FIG. 2, and is an ATM cell used in a UNI (User Network Interface) of ATM (Asynchronous Transfer Mode) method recommended by CCITT. For 53 octets, the cycle code block is 5 bytes (40 bits), the number of confirmation bits is 1 byte (8 bits), and the generator polynomial is G (x) = x ⁸ + x ¹ + x + 1 and 2 In decimal, the number is 100000111. Thus, the compensated polynomial C (x, B _s ) x shifts s + 1 bit shifts in the upper bit direction by remaining x ⁵ + x ⁴ +1 modulated by x ³⁹ divided by 2 into x ⁸ + x ² + x + 1. B _s x ^s (x ⁵ + x ⁴ + 1) x and B _s x ^s (1100010) when expressed in binary. That is, the compensated polynomial (C (x, 1) x) is obtained by dividing x ³⁹ by x ⁸ + x ² + x + 1 and modulating the remainder x ⁵ + x ⁴ +1 by one bit in the higher bit direction. ⁵ + x ⁴ + 1} x and 1100010 when represented in binary.

In the figure, 300 is a 5-byte shift register, 319 to 326 are D flip-flops, 31 to 54 are exclusive OR gates for subtracting 2 to the compensation polynomial module, 330 to 353 are exclusive OR gates for 2 division with the generated polynomial module, and 310 are compensation The polynomial driving circuit 390 represents eight input OR gates, respectively.

The compensation polynomial driving circuit 310 is simply driven from the precomputed result using the output of a 5-byte shift register, and the compensation polynomial driving circuit and the generating polynomial driving circuit and the compensation polynomial modulo 2 subtraction and generating polynomial modulo 2 In the divide circuit, the '0' term is omitted because it is not meaningful.

Next, the operation principle will be described in detail.

The data byte string is input to the data input terminal of the 5 byte shift register 300 and the data input terminals of the D flip-flops of the polynomial modulo 2 subtraction and generation polynomial modulo 2 divide circuit. Since the 5-byte shift register is initially initialized to logic level '0', it outputs '0' during 5-byte intervals.

Therefore, during the 5-byte unit interval, the compensation polynomial modulo 2 subtracting 31 to 54 and the generating polynomial modulo 2 dividing circuit 330 to 353 are not affected by the compensation polynomial driving circuit 310. The K polynomial modulo 2 subtraction (31 to 54) and the generating polynomial modulo 2 dividing circuit (330 to 353) at the moment instantiate the most significant bit of the byte input at the moment K-5 after a 5-byte interval. Create a block with the most significant bit of the block and the least significant bit of the byte input at the moment K-1 as the least significant bit of the block. Compensate by making the remainder divided by the polynomial 10000011 2 as the upper bit and the byte input at the moment K as the lower bit. Subtract and create 2 with polynomial module You want to divide 2 with the polynomial module again. At this time, if the most significant bit of the byte input at the moment K-5 is the logic level '0', the difference of the data to be calculated by the compensation polynomial modulo 2 subtraction (31 to 54) and the generation polynomial modulo 2 division circuit (330 to 353). Performs division by modulus with a decimal number 100000111, which is a generation polynomial from the bit, whereas if the most significant bit of the byte input at the moment K-5 is the logic level '1', compensated polynomial modulo 2 (31 to 54) subtraction and generation polynomial module Generate polynomial after performing modulo 2 subtraction with the x ⁷ (x ⁵ + x ⁴ +1) x compensated polynomial driven in the compensation polynomial generation circuit from the upper bits of the data to be computed by the two division circuits 330 to 353 Perform a two division into the modulus with the decimal number 100000111.

Then, if the next most significant bit of the input byte at the moment K-5 is the logic level '0', a polynomial is generated for the remainder of the result of the operation as the upper bit and the next bit of the input byte data as the least significant bit. If the modulus is divided by modulus 100000111, and the most significant bit of the byte input at the time of K-5 is the logic level '1', the polynomial (the rest of the result of the operation being performed is the upper bit and is input). A polynomial that is a generation polynomial after performing modulo 2 subtraction with the x ⁶ (x ⁵ + x ⁴ +1) x compensated polynomial driven in the compensation polynomial generation circuit for the next bit of the byte data as the least significant bit). The process of performing division by 2 modulo K-5 parallel to the least significant bit of the input byte at the moment / lowest bit of the input byte. Performed with) repeat. Accordingly, the inputs of the D flip-flops 319 to 326 of the compensated polynomial modulo 2 subtractive (31 to 54) and the generated polynomial modulo 2 dividing circuits (330 to 353) at the moment K are input from the moment K-4 to the moment K. Block represents the remainder divided by two with a decimal number 100000111. If the inputs of the D flip-flops 319 to 326 are not all logic level '0' (the rest is not 0), the block inputted from the moment K-4 to the moment K according to the definition of the CRC is a cyclic code block. This is not it.

If there is a bit of logic level '1' among the bits of the byte (high byte at the moment K) input at the moment K-4 at the output of the 5 byte shift register 300 at the moment K + 1, the sequential corresponding to the bit Compute a polynomial with the remainder of the instantaneous K moment at the moment of operation as modulus polynomial, and then subtract modulo 2 into the modulated polynomial. Bit at the logic level '0' among the bits of the byte of the 5 byte shift register 300 at the instant of You can only subdivide a polynomial into lower polynomials.

Eventually, the CRC function is executed at byte intervals, and when a cyclic code block is formed, the inputs of the D flip-flops 319 to 326 of the compensating polynomial modulo 2 subtraction (31 to 54) and the generating polynomial modulo 2 division circuit (330 to 353). In these cases, the logic level '0' becomes the so-called syndrome '0', and the output of the eight-input OR gate 390 becomes the logic level '0'. Although not dealt with in the present invention, a fake cyclic code block can be generated because an input data bit can have an arbitrary value, which can detect a fake cyclic code block as if the detected cyclic code block is periodic.

The present invention can be replaced with the conventional CRC apparatus because the boundary of the cyclic code block of the input data can be searched by byte interval using the circuit configuration as described above to distinguish not only the block boundary but also the CRC sub-function. It has the following distinctive effects.

First, even if the boundary of the cyclic code block is changed, the implementation is simplified because the cyclic code is decoded by the conventional calculation result and the compensation formula.

Second, since the cyclic code is decoded at byte intervals, the block synchronization function can be performed.

Third, since the input data is stored as the size of the block, it is not necessary to use a data delay circuit separately to match the timing of the block synchronization detection signal and the block data.

Claims (1)

N (N = n / 8) s, which is an n (8-fold natural number with n: r + m) bit consisting of a check bit of r (r: natural) bits and a message bit of m (m: 8-fold natural numbers greater than m: r) bits The block polynomial of bytes is generated by G (x) = x ^r +…. … In CRC apparatus using +1; Initially, all N bytes are initialized to a logic level '0', and the byte data output side of the N byte shift register means 21 and the N byte shift register means 21, which outputs the byte string to be decoded by N byte shift. For each bit (B _s x ^s ) of the byte output from the N-byte shift register means, generate X ^n-1 , which is the most significant bit of the N-byte block code, by dividing the remainder by dividing into two by the module polynomial. C (X, B _s ) x = B _s x ^s (a _r-1 x ^r-2 + a _r-2 x ^r-2 +... Shifted one bit higher bit direction) … Compensation polynomial driving means 22 for driving a compensation polynomial of + a ₂ x ^r2 + a ₁ x ^r1 + a ₀ } x, the byte array to be decoded in connection with the compensation polynomial driving means and the byte data external input terminal. Inputting subtracted modulo 2 by C (x, B ₇ ) x polynomial driven by the compensated polynomial driving means 22 in the order of higher bits, and then performing 2 dividing modulo by the generated polynomial G (x). After the remaining remainder is modulated by C (x, B ₆ ) x polynomial 2 driven by the compensation polynomial driving means 22 and modulo 2 divided by the generated polynomial G (x), respectively, sequentially in bit units. 2 subtracted by the compensated polynomial module which repeatedly executes the C (x, B ₀ ) x polynomial driven by the compensation polynomial driving means 22 for 1 byte, and outputs the result to the outside when the remainder is '0'. And generate the divisor means 23 by the polynomial modulo A cyclic margin inspection apparatus capable of distinguishing block boundaries in byte synchronized data.