KR950010771B1 - Crc apparatus of bound area of bite syncronized data - Google Patents

Abstract

an N byte shift resistor for shifting byte columns to be decoded by N bytes; a compensation polynomial driver connected to the N byte shift resistor, fro driving a compensation polynomial, if a bit of the byte outputted from the N byte shift resistor is Bsxs; a compensation polynomial modulor 2 subtracter for modulor 2 subtracting data inputted in byte unit from an output terminal of the N byte shift resistor to output the result to a generator polynomial; and a compensation polynomial modulor 2 demultiplier for modulor 2 demultiplying data inputted in byte unit connected to an input terminal of the N byte shift resistor and the compensation polynomial modulor 2 subtracter to output the result to the compensation polynomial modulor 2 subtracter.

Description

CRC (Circulation Free Inspection) device that can distinguish block boundary from byte synchronized data

1 is a block diagram of a CRC (Circulation Free Inspection) apparatus that can distinguish a conventional block boundary.

2 is a CRC (Circulation Free Inspection) apparatus capable of distinguishing block boundaries according to the present invention.

3 is a detailed configuration diagram of a CRC (circulation free space inspection) apparatus capable of classifying block boundaries according to the present invention.

* Explanation of symbols for main parts of the drawings

11: CRC calculator 12: delay means

13 CRC calculation derivation means 14 coincidence detection means

21: N byte shift register 22: Compensated polynomial driver

23: Compensation polynomial modulo 2 subtraction 24: Generation polynomial modulo 2 division

300: 5-byte shift register 310: compensated polynomial driver

311-318: D flip-flop

321-348: Exclusive OR Gate for Divide Compensation Polynomial Modulo 2

390: 8-input OR gate

According to the present invention, when data inputted in Cyclie Redundancy Check (CRC), which is one of error detection and correction methods using a cyclic code, is byte-synchronized but the block boundary of the cyclic code is unknown The present invention relates to a CRC device that outputs the boundary of a block by continuously performing a byte-by-byte byte sequence.

Conventional CRC devices are configured to operate in a given state, so that in order to know a block boundary, whenever a byte sequence constituting a block is sequentially changed, that is, a code word constituting the block is directed to the most significant byte direction. Whenever a block is moved by one byte and the new least significant byte is formed, the operation of repeating the operation of the number of bytes constituting the block has to be repeated. (Tong-Bi Pei, "High-Speed Parallel CRC Circuits in VLSI", IEEE Transactions on Comm, Vol, 40, No. 4, April 1992).

The apparatus shown in FIG. 1 is a "HEC synchronizer in the CRC calculation method and the ATM switching method" according to the conventional Japanese Patent Laid-Open No. 4-284753, as shown in the drawing. 12), the CRC arithmetic derivative 13 and the coincidence detector 14.

The conventional CRC (circular free space inspection) device that can distinguish the block boundary shown in FIG. 1 can avoid the repetitive calculation, which is the above problem, but can reduce the amount of hardware compared to the conventional one. Since the delay is compared with the result of the CRC operation on the new block boundary, the circuit comparing the calculated result is additionally inserted and the result to be calculated is not known until after the least significant byte of the block is output.

Accordingly, the present invention is to fundamentally solve the above-mentioned problems, and even if the byte strings constituting the block are sequentially changed, only the newly added byte number or block is performed without the operation of the number of bytes constituting the block. It is an object of the present invention to provide a CRC device that distinguishes a block boundary by performing an operation for the number of bytes excluded from and outputs an operation result before the start of the block.

In order to achieve the above object, the present invention provides a bit of n (n is an 8-fold natural number of r + m) consisting of a confirmation bit of r (r is a natural number) bit and a message bit of m (8-fold natural number greater than m and r) bits. A generator polynominal with a block code of N (N = n / 8) bytes is a CRC device using G (x) = x ^r + ... +1. Initially, the logical level '0' is N bytes. Is initialized and connected to the N-byte shift register means for outputting the byte string to be decoded by N-byte shift, the N-byte shift register means, and the bit of the byte output from the N-byte shift register means is B _s x ^s (S is an integer from 0 to 7, B _S is a coefficient with 0 or 1, B ₇ is 0 or 1 as the coefficient of the most significant bit, and 0 or 1 as the B ₀ least significant bit coefficient, and each byte (B _s x ^s Parallel by configuring the compensation polynomial for each bit Compensation polynomial driving means for driving the compensation polynomial in units, Compensation polynomial Modulo 2 subtraction means for inputting data to be decoded in bytes and performing modulo 2 subtraction with the polynomial driven by the compensation polynomial driving means in bytes. And a generating polynomial modulo 2 dividing means connected to the compensating polynomial modulo 2 subtracting means for performing modulo 2 dividing with the generated mononomial G (X) and outputting the remainder to the compensating polynomial modulo 2 subtracting means. .

Hereinafter, in order to explain the operation principle of the invention by a mathematical interpretation in detail as a bit unit operation as follows.

The size of the block is n bits, transmitted as the G (x) -generated polynomial, and the n-bit block is T _k (x) at any moment k that does not know the block boundary. When the input bit is a _k and the bit input at k + 1 moment in the bit string is a _{k + 1} , if the n-bit block is T _{k + 1} (x) at the moment _{k + 1,} the n bits at the moment k Block is

T _k (x) = a _kn-1 x ^n-1 + B _k (x) + a _k

Where a _kn-1 x ^n-1 is the most significant bit of the n-bit block at the moment k and a _kn-1 is the bit entered (n-1 times before k for the moment). A _k is the least significant bit of the n-bit block at the moment _k , and means the bit input at the moment _k , and B _k (x) is the remaining bits except the most significant bit and the most significant bit in the n bit block at the moment k. Also, the n-bit block at k + 1 moments

T _{k + 1} (x) = a _kn x ^n-1 + B _{k + 1} (x) + a _{k + 1}

Where a _kn x ^n-1 is the most significant bit of the n-bit block at the moment k + 1 and a _kn is the bit entered at the moment kn, and a _{k + 1} is the bit of the n-bit block at the moment k + 1. It is the least significant bit and means the bit input at the k + 1 moment, and B _{k + 1} (x) is the remaining bits except the most significant bit and the least significant bit in the n-bit block at the k + 1 moment. Generating n-bit blocks at any k moments and modulating 2 by the polynomial G (x) yields {a _kn-1 x ^nl + B _k (x) + a _k } / G (x) and {a _{kn -1} x ^n-1 + B _k (x) + a _k / G (x) is set to Rr (x) and a _kn -x ^nl / G (x) is set to C _k (x) { The remainder of B _k (x) + a _k ) / G (x) is R _k (x) -C _k (x). However, since the n-bit block at the moment k + 1 is T _{k + 1} (x) = (B _k (x) + a _k ) x + a _{k + 1} , the n-bit block is generated at the k + 1 instant. The result of modulo 2 division by x) is [{B _k (x) + a _k } x] / G (x) + a _{k + 1} / G (x) and [{B _k (x) + a _k }] Since the remainder of G (x) is {R _k (x) -C _k (x)} x, the remainder of T _{k + 1} / G (x) is {R _k (x) -C _k (x) } The same as the remainder of x + a _{k + 1} / G (x).

Reference will now be made in detail to one embodiment of the present invention with reference to the accompanying drawings.

2 is a schematic block diagram of the present invention, in which 21 represents an N-byte shift register, 22 represents a compensated polynomial driver, 23 represents a compensated polynomial modulo 2 subtractor, and 24 represents a generated polynomial modulo 2 divider, respectively. .

As shown in FIG. 2, the CRC apparatus capable of classifying block boundaries in byte-synchronized data according to the present invention includes an N-byte shift register 21, a compensation polynomial driver 22, and a compensation polynomial modulo 2 subtraction 23. And a generation polynomial modulo 2 divide (24).

The 5-byte shift register 21 is initially initialized with a logic level of '0', and all 5 bytes are initialized. The bytes to be decoded are sequentially shifted one byte at a time, storing 5 bytes of byte strings, and at the time k + 5. Prints the bytes that were entered at the moment in k.

The compensated polynomial driver 22 is connected to the 5-byte shift register 21 so that the bits of the byte output from the 5-byte shift register 21 are B _s x ^s (s is an integer from 0 to 7 as B). _s , is a coefficient having 0 or 1, B ₇ is 0 or 1 as the coefficient of the most significant bit, and B ₀ is 0 or 1) as the least significant bit coefficient. When CRC operation is performed on the header part of the 5-byte block code for each bit (B _s x ^s ) constituting the byte, when only one byte of the 8-bit data is 1 in the operation, The operation result of <is shown in <Table 1>.

TABLE 1

The compensated polynomial modulo 2 subtractor 23 is connected to the compensated polynomial driver 22 to byte data driven in bytes by the compensated polynomial driver 22 for the byte string to be decoded at each byte interval. After modulo 2 subtraction, the input byte and the generated polynomial are transferred to the modulo 2 operation circuit as the generated polynomial for modulo 2 operation.

FIG. 3 is a detailed configuration diagram of a CRC device capable of classifying block boundaries in the site-synchronized data of FIG. 2. FIG. 3 shows an ATM cell used in a user network interface (UN) of an ATM (Asynchronous Transfer Mode) method recommended by CCITT. The cyclic code is 53 octets. The cyclic code block is 5 bytes (40 bits), the number of confirmation bits is 1 byte (8 bits), and the generated polynomial is G (x) = x ⁸ + x ² + x + It is 1 and expressed in binary, it is prime number which is 100000111. Thus, the compensated polynomial (C (x, B _s ) x) is the s + 1 bit in the higher bit direction of x ⁵ + x ⁴ +1, the remainder of dividing x ³⁹ by x ⁸ + x ² + x + 1 modulo 2 a shift in which _{^{B s x s {x 5 +}} x 4 +1) and if indicated by a binary number B ^_s x _s (1100010). That is, the compensated polynomial (C (x, 1) x) shifts x ⁵ + x ⁴ +1 by one bit into the upper bit direction, the remainder of dividing x ³⁹ by x ⁸ + x ² + x + l. x ⁵ + x ⁴ +1} x and 1100010 when represented in binary. If this is expressed as a compensation polynomial in bytes, it is as shown in Table 1 above.

In FIG. 3, 300 is a 5-byte shift register, 311 to 318 are D flip-flops, 321 to 348 are exclusive OR gates for subtracting the compensated polynomial modulo 2, and 351 to 374 are exclusive OR gates for division to the generated polynomial modulo 2, 310 Is a compensated polynomial driving circuit, and 390 is an eight input OR gate.

In FIG. 3, the compensation polynomial driving circuit 310 is simply driven using the output of the 5-byte shift register 300 from the precomputed result, and the compensation polynomial driving circuit, the generated polynomial driving circuit and the compensation polynomial modulo 2 Subtraction and Generation In the polynomial modulo 2 division circuit, the term '0' is omitted because it is meaningless.

The principle of operation will be described in detail using the drawings of FIG.

The data byte string is input to the data input terminal of the 5-byte shift register 300 and the input terminal of the generation polynomial modulo dividing circuit, respectively. Since the 5-byte shift register is initially initialized to logic level '0', it outputs '0' during the 5-byte interval. Therefore, during the 5-byte unit interval, the compensated polynomial modulo 2 subtractions 321 to 348 and the generated polynomial modulo 2 divide circuits 351 to 374 are not affected by the compensated polynomial driving circuit 310.

The k-compensated polynomial modulo 2 subtraction (321 to 348) and the generated polynomial modulo 2 divide circuit (351 to 374) at the instant of the k are first divided into bytes of the block at the time of k-5 after a 5-byte interval. Create a block with the most significant byte and the least significant byte of the input byte (8 bits) at k-1. Subtract modulo 2 by the polynomial 10000011 and subtract and generate the remainder of the input byte and the compensated polynomial module 2 in k instants. Attempt to divide the polynomial by 2 again. At this time, if each bit constituting the input byte at the time k-5 is logic level '0', data to be calculated by the compensating polynomial modulo 2 subtraction (321 to 348) and the generating polynomial modulo 2 division circuit (351 to 374). Generate in bytes. Modulo 2 divide by the decimal number 100000111. Then, if the most significant bit of the byte input at the moment k-5 is the logic level '0', it is generated for a polynomial that makes the rest of the result of the operation performed as the upper bit and the next bit of the input byte data as the least significant bit. If the modulo 2 division is performed by the decimal number 100000111, which is the polynomial, while the most significant bit of the byte input at the time k-5 is the logic level '1', the polynomial (the rest of the result of the operation and the input byte data) To perform the modulo 2 division with the generated polynomial prime number 100000111 after performing modulo 2 subtraction with the compensated polynomial driven by the compensated polynomial generation circuit. It executes in parallel (byte unit) with respect to bytes.

Accordingly, the inputs of the compensated polynomial modulo 2 subtractions 321 to 318 at the instant k represent the remainder obtained by dividing the block inputted from the instant k-4 to the instant k into the decimal number 100000111. If each of the inputs of the D flip-flops 311 to 318 are not all at the logic level '0' (the rest is not 0), the block inputted from the moment k-4 to the moment k according to the CRC definition is not a cyclic code block.

Eventually, the CRC function is executed at byte intervals, and when a cyclic code block is formed, the inputs of the D flip-flops 311 to 318 of the compensating polynomial modulo 2 subtraction circuits 321 to 348 are all logic level '0' (so-called syndromes). syndrome) becomes '0'), and the output of the eight-input OR gate 390 becomes a logic level '0'.

The present invention can be replaced with the conventional CRC apparatus because the boundary of the cyclic code block of the input data can be searched at byte intervals to distinguish not only the block boundary but also the CRC sub-function. It has the following distinctive effects.

First, even if the boundary of the cyclic code block is changed, the implementation is simplified because the cyclic code is decoded by the conventional calculation result and the compensation formula.

Second, since the cyclic code is decoded at byte intervals, the block synchronization function can be performed.

Third, since the input data is stored as the size of the block, it is not necessary to use the data delay circuit according to the timing between the block synchronization detection signal and the block data.

Claims (2)

N (N = n / 8) bytes, n (n is an eight-fold natural number of r + m), consisting of a check bit of r (r is a natural number) bit and a message bit of m (eight-fold natural number greater than m and r) bits The generator poyynominal is a CRC device using G (x) = x ^r + ... ... +1. Initially, all N bytes are initialized to a logic level of '0' and the byte to be decoded. An N-byte shift register means for shifting a column by N-byte shifts, and a bit of a byte output from the N-byte shift register means, wherein the bit of the byte output from the N-byte shift register means is equal to B _s x ^s (s is 0 to 7). Integer B _s is a coefficient with 0 or 1, B ₇ is 0 or 1 as the coefficient of the most significant bit, 0 or 1 as the B ₀ least significant bit coefficient, and N bytes of block code for each byte (B _s x ^s ). Create x ^n-1 , the most significant bit of, and divide it by modulo 2 by the polynomial. Compensation polynomial driving means for driving the compensation polynomial which shifts the rest to the s + 1 bit higher bit direction, and generates data input in the unit of byte at the output of the N-byte shift register. Compensation polynomial modulo 2 subtraction means for subtracting modulo 2 with the compensation polynomial driven by the compensation polynomial driving means and inputting the generated polynomial G (x), and the input end of the N-byte shift register and the compensation polynomial modulo 2 Compute the byte data output from the N-byte shift register by dividing the data in the byte unit connected to the subtraction means by dividing it into modulo 2 by the polynomial G (x). Generate the remainder of the row 2 operation. Compute the polynomial by modulo 2 operation with the unary G (x). Dyulro 2 CRC apparatus comprising a second dividing means to a generator polynomial module for outputting the subtraction means. The CRC apparatus of claim 1, wherein the N-byte shift register is configured of a 5-byte shift register.