JPS6352477A - Manufacture of non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate a residual substance at a side wall of a selection gate and a floating gate after an etching process of phosphorus-doped polysilicon by a method wherein an insulating substance is filled between the selection gate and the floating gate so that a flat surface can be obtained. CONSTITUTION:A gate 5 of a selection transistor and a floating gate 6 of a memory transistor are formed. Then, a CVD silicon oxide film 7 and a resist film 8 for flattening use are formed successively so that a flat surface can be obtained by reactive ion etching in such a way that the CVD silicon oxide film 7 is left in a region where the first phosphorus-doped polysilicon layer has been etched. Through this constitution, it is possible to eliminate a residual substance at a side wall of a selection gate and a floating gate without increasing the size of a cell after a conductive material to be used for a control gate has been etched.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device having a floating gate, and particularly to a device in which electrical writing and erasing can be performed for each memory unit. Regarding 2.

(Prior art) Positive or negative charge is injected into a floating gate electrode that is electrically insulated from the outside to change the conductive state of an insulated gate type (MOS) transistor.
Nonvolatile semiconductor devices for storing 1P or "O" information are already known.

In particular, it has a floating gate electrode insulated from the outside, and further has a control gate electrode and a pole provided so as to cover the floating gate. Nonvolatile memory cells consisting of ordinary MOS transistors for address selection are widely known.

In this memory cell, part of the drain of the storage element overlaps part of the floating gate via an insulating film thinner than the gate insulating film, and the FOWler flowing through this thin insulating film
- Filling/erasing is performed by NOrdheim current.

That is, during writing, the address selection MOS transistor (N
A high positive voltage is applied to the gate of the channel Tr, and this transistor is turned on (at this time, the drain of the address selection MOS transistor is kept at the ground potential). On the other hand, a high voltage is applied to the control gate of the storage transistor as well as to the address selection transistor. At this time,
A high electric field is applied to the thin insulating film, and electrons are injected from the drain to the floating gate. During erasing, a high voltage is applied to the gate and drain of the address selection MOS transistor, and the control gate of the storage transistor is set to the ground voltage. At this time,
The address selection transistor is turned on, a high voltage is also applied to the drain of the storage transistor, and a high electric field in the opposite direction to the input and output is applied to the thin insulating film, causing electrons to flow from the floating gate to the train.

The source of the storage transistor is at OV both during programming and erasing. During erasing in which a high voltage is applied to the drain of the selection transistor, the potential of the storage transistor may be set to a slightly positive potential. When reading, the conductance is read with the gates of both transistors and the train of the selection transistor set to positive voltage, and the source of the storage transistor set to OV.

As a method for forming such a memory cell, for example, a method as shown in FIG. 2 is known.

In FIG. 2, a gate insulator WOE and phosphorus-doped polysilicon are sequentially formed on a substrate, and a desired resist pattern (2) is formed using a light exposure technique.

Using this resist pattern as a mask, the phosphorus-doped polysilicon is etched to form the gate (T) of the selection transistor and the floating gate (A) of the storage transistor (FIG. 2(a)).

Thereafter, the resist pattern is removed, and a phosphorus-doped polysilicon layer (a) of the rear cylinder 2 with an insulating film formed thereon is formed by thermal oxidation. Next, a resist pattern (a) is formed using a light exposure technique (FIG. 2 (g)).

Using this resist pattern as a mask, the phosphorus-doped polysilicon layer is etched to form the control gate (23) of the storage transistor, and after removing the resist (Fig. 2(C)), the phosphorous-doped polysilicon layer is etched. A memory cell is completed according to the process.

However, the above manufacturing method has encountered the following problems.

When the second phosphorus-doped polysilicon layer is processed by anisotropic etching, the second phosphorus-doped polysilicon layer remains on the gate of the selection transistor and the sidewalls of the floating gate.
(see Figure (c)-(24)), which poses a problem in terms of reliability. Furthermore, when etching is performed by isotropic etching, there is a problem in designing with so-called side etching in mind, which leads to an increase in cell size.

(Problems to be Solved by the Invention) In view of the above-mentioned problems, the present invention does not leave etching residues of phosphorus-doped polysilicon on the sidewalls of the selection gate and floating gate, thus achieving excellent reliability and increasing cell size. The purpose of the present invention is to provide an excellent nonvolatile memory cell with no problems.

(Structure of the Invention) (Means for Solving the Problems) The present invention embeds an insulator between the selection gate and the floating gate to planarize it, so that even if the control gate is processed by anisotropic etching, it can be selected. By eliminating phosphorus-doped polysilicon from remaining on the sides of the gate and floating gate, a nonvolatile memory cell with excellent reliability and no increase in cell size is provided.

(Function) By using the present invention, it has become possible to solve the conventional problem of phosphorous-doped polysilicon remaining on the sidewalls of the selection gate and floating gate without increasing the cell size.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to FIG.

On a p-type silicon substrate ω, a gate thermally tempered film ① and a first phosphorus-doped polysilicon layer (3) are formed in sequence, and a desired resist pattern ←) is formed using light exposure technology (Fig. 1 ←). ). Here, the gate oxide film 1 is made thinner at the drain part of the storage transistor than at other parts. This entire thin portion may be located under the gate, and n+jp may be formed in advance on the substrate below it to be connected to the drain diffusion layer in a later process.

Furthermore, memory operation is possible even without providing locally thin portions in the gate oxide film (1).

Using the resist pattern (a) as a mask, the first phosphorus-doped polysilicon layer is etched using reactive ion etching technology. As a result, the gate of the selection transistor and the floating gate of the storage transistor (
a is formed.

Next, a CVD silicon oxide film layer (■) and a planarization resist film (
8) is sequentially formed (Fig. 1(C)), and the surface is planarized by leaving a CVD silicon oxide film 2 in the region where the first phosphorus-doped polysilicon layer has been etched using reactive ion etching technology (Fig. 1(C)). 1).

Next, a silicon oxide film (9) is formed on the floating gate θ and the selection gate (2) by thermal oxidation or the like, and then a second phosphorus-doped polysilicon layer (1Φ) is formed (see FIG. 1).
e)). Subsequently, a desired resist pattern (6) is formed using a light exposure technique, and then the second phosphorus-doped polysilicon layer is etched using a reactive ion etching technique to form a control gate Q2). The processing of the area is completed (Fig. 1 (0)). Next, the resist pattern (2) is peeled off, and n+ type source/drain regions are formed by ion implantation according to the normal MOS transistor manufacturing process (03). Oxidation O◇, contact hole opening, M wiring OΦ, etc. are performed to complete the nonvolatile memory cell. The operation method of such a memory cell is the same as described above. In addition to the silicon oxide film, the insulating film formed between the floating gate and the control gate may be made of a three-layer structure of silicon oxide film-silicon nitride film-silicon oxide film, or silicon oxide film-silicon nitride film. The membrane may have a two-layer groove structure, or may be made of tantalum oxide or the like.

In addition to the CVD silicon oxide film, the insulating film buried between the floating gate and the selection gate may be a plasma silicon oxide film, etc., and the planarization method is a reactive ion etching technique after applying a planarization resist. In addition to the etching method, for example, a bias sputtering technique may be used for planarization without departing from the spirit of the present invention.

Furthermore, the present invention is effective even when a material other than phosphorus-doped polysilicon is used as the gate material, such as a high melting point metal such as tungsten, tungsten silicide, or molybdenum silicide.

〔Effect of the invention〕

By using the present invention, it has become possible to prevent etching residues of the conductive material used for the select gate and floating gate sidewalls on the side walls of the select gate and floating gate without increasing the cell size, which was a problem in the prior art.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the present invention, and FIG. 2 is a process sectional view showing an example using a conventional method. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate 2... Gate oxide film 3... First phosphorus doped polysilicon layer 4... Resist pattern 5... Selection gate 6... Floating gate 7... CVD Silicon oxide film 8...Resist for flattening 9...Silicon oxide film 10...
Second phosphorous-doped polysilicon layer 11...Resist pattern 12...Control gate 13...Source/drain region 14...Silicon oxide film 15...M wiring 1
6... Gate oxide film 17... Resist pattern 18... Selection gate 19... Floating gate 20... Silicon oxide film 21... Second phosphorous doped polysilicon, 122...
...Resist pattern 23...Control gate 24
...Participant for the remaining portion of the second phosphorus-doped polysilicon layer after etching Patent attorney Noriyuki Chika Kidaio Takehana (a) Cb) (C) Figure l (e) Figure l (a) ) (b) Figure 2

Claims (1)

[Claims] A nonvolatile semiconductor memory device in which memory cells having floating gates are integrated on a semiconductor substrate, and each memory cell has a source and a drain formed in isolation from each other on the semiconductor substrate, and a drain between the source and drain. a floating gate formed on the channel region of the floating gate with an insulating film interposed therebetween, a rewrite electrode placed opposite to the floating gate with an extremely thin insulating film interposed therebetween, and one or more controls capacitively coupled to the floating gate. Only a selected memory cell is provided with a gate, and a potential relationship between the rewriting electrode and the control gate is set, and the stored content is changed by transfer of charge between the rewriting electrode and the floating gate via the ultra-thin insulating film. When manufacturing a rewriteable nonvolatile semiconductor memory, the steps include forming the floating gate and the selection gate, and burying a first insulating film between the floating gate and the selection gate to flatten the step. A method for manufacturing a nonvolatile semiconductor memory device, comprising the steps of: forming the control gate on the floating gate via a second insulating film.