JPS6350872B2 - - Google Patents
Info
- Publication number
- JPS6350872B2 JPS6350872B2 JP54160693A JP16069379A JPS6350872B2 JP S6350872 B2 JPS6350872 B2 JP S6350872B2 JP 54160693 A JP54160693 A JP 54160693A JP 16069379 A JP16069379 A JP 16069379A JP S6350872 B2 JPS6350872 B2 JP S6350872B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- insulating film
- drain
- drain region
- field plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000005684 electric field Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Description
【発明の詳細な説明】
本発明は高耐圧MOS電界効果トランジスタ
（以下高耐圧MOSFETと略す）に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage MOS field effect transistor (hereinafter abbreviated as high voltage MOSFET).
MOSFETの高耐圧化を図る一つの方法とし
て、ゲート電極端の電界集中を防ぐために、ドレ
イン領域の周辺にドレイン領域の一部として同一
導電型の高抵抗層を設ける方法が試みられてい
る。第１図はこの種の高耐圧MOSFETの断面図
を示したものである。図に於て１はＰ型基板で、
該基板１にN+ソース領域２及びN+ドレイン領域
３が夫々形成されているが、ソース領域２の周囲
には自己整合プロセスによつてMOSFETのゲー
トチヤネルのためのP+領域４が設けられ、また
ドレイン領域３の周囲にはゲート電極端の電界集
中を防ぐためにドレイン領域の一部として同一導
電型の高抵抗層５が設けられている。上記のよう
な不純物拡散がなされた基板１に対して、該基板
１の表面には、ソース領域２及びドレイン領域３
に夫々接続されたソース電極６及びドレイン電極
７がAl或いは多結晶Si等によつて設けられてい
るが、いずれの電極も各領域に電気的接続するだ
けでなく、導体が周辺基板上の絶縁膜８に延びた
フイールドプレート部６′，７′が一体的に設けら
れている。ソース電極６から延びたフイールドプ
レート６′はゲート電極端の電界を緩和する役目
を果たし、ドレイン電極７から延びたフイールド
プレート７′はドレインのN+−N-境界付近での
電界の集中を緩和する。図中９はチヤネル領域４
上に設けられたゲート電極である。 One method of increasing the withstand voltage of MOSFETs is to provide a high resistance layer of the same conductivity type as part of the drain region around the drain region in order to prevent electric field concentration at the end of the gate electrode. FIG. 1 shows a cross-sectional view of this type of high voltage MOSFET. In the figure, 1 is a P-type substrate,
An N + source region 2 and an N + drain region 3 are formed on the substrate 1, and a P + region 4 for a gate channel of the MOSFET is provided around the source region 2 by a self-alignment process. Further, around the drain region 3, a high resistance layer 5 of the same conductivity type is provided as a part of the drain region in order to prevent electric field concentration at the end of the gate electrode. A source region 2 and a drain region 3 are formed on the surface of the substrate 1 in which the impurity is diffused as described above.
A source electrode 6 and a drain electrode 7, which are connected to each other, are made of Al, polycrystalline Si, etc., but each electrode is not only electrically connected to each region, but also has a conductor connected to an insulating layer on the peripheral substrate. Field plate portions 6', 7' extending to the membrane 8 are integrally provided. A field plate 6' extending from the source electrode 6 serves to alleviate the electric field at the end of the gate electrode, and a field plate 7' extending from the drain electrode 7 alleviates the concentration of the electric field near the N + -N - boundary of the drain. do. 9 in the figure is channel area 4
This is the gate electrode provided above.
ここで上記各フイールドプレート６′，７′は互
いに延ばし過ぎると、フイールドプレート６′が
ドレイン領域３に及ぼす逆フイールドプレート効
果及びフイールドプレート７′のゲート電極端に
及ぼす逆フイールドプレート効果が顕著になり、
逆に耐圧を低下させる結果になる。 If the field plates 6' and 7' are extended too much, the reverse field plate effect that the field plate 6' has on the drain region 3 and the reverse field plate effect that the field plate 7' has on the end of the gate electrode becomes noticeable. ,
On the contrary, this results in a decrease in breakdown voltage.
また上記構造のMOSFETは、両側から延びて
きたフイールドプレート６′，７′間に、Al或い
は多結晶Siのような導体で被覆されない高抵抗層
５の領域が生じることになり、該導体被覆されな
い高抵抗層５の領域は外部電荷の影響を受けてオ
ン耐圧、ドレイン電流、及びRON等の電気的特性
が変動する欠点があつた。 Further, in the MOSFET having the above structure, there is a region of the high resistance layer 5 that is not covered with a conductor such as Al or polycrystalline Si between the field plates 6' and 7' extending from both sides, and the area is not covered with the conductor. The region of the high-resistance layer 5 has a disadvantage in that electrical characteristics such as on-breakdown voltage, drain current, and R ON vary due to the influence of external charges.
本発明は上記従来の高耐圧MOSFETにおける
欠点を除去し、耐圧特性にすぐれ且つ信頼性の高
いMOSFETを提供するもので、図面を用いて実
施例を詳細に説明する。 The present invention eliminates the drawbacks of the conventional high voltage MOSFETs mentioned above and provides a MOSFET with excellent voltage resistance characteristics and high reliability.Examples will be described in detail with reference to the drawings.
第２図ａにおいてP-基板１には前記従来
MOSFETと同様にソース領域２、ドレイン領域
３、P+チヤネル領域４及びN-高抵抗層５が形成
され、ソース領域２にはソース電極６が、ドレイ
ン領域３にはドレイン電極７が電気的接続され、
その他の基板表面は絶縁膜８で被覆されている。
尚９はチヤネル領域４上に設けられた所定膜厚の
ゲート酸化膜上に形成されたゲート電極である。
ここで上記従来の欠点を除去するために、ソース
電極側から延ばしたフイールドプレートとドレイ
ン電極側から延ばしたフイールドプレートは互い
に延ばし過ぎないで、しかも第１図のＡのような
導体被覆されない領域が形成されないようにする
ため高抵抗層領域上の中央部付近で上記両フイー
ルドプレートが絶縁層を介して一部重なり合うよ
うに設けられている。即ち第２図ａに示した実施
例はソース電極側から延ばしたフイールドプレー
トとしてソース電極と一体的に設けられたフイー
ルドプレート６′が形成され、ドレイン電極側か
ら延ばしたフイールドプレートとして被覆導体１
０1が、フイールドプレート６′，７′面に対して
基板表面に近い絶縁層中に設けられ、ゲート電極
９を作成する工程を利用して同時に形成され、ド
レイン領域３に接続された導体の延長として設け
られている。第２図ｂ及びｃも同様に被覆導体１
０2，１０3が基板表面に近い絶縁膜中に形成され
るが、ドレイン或いはソース電極の延長部として
設けられるものではなく、領域Ａを被う島状に被
覆導体１０2，１０3が形成され、該被覆導体をソ
ース或いはドレインのフイールドプレート６′，
７′を作成する工程でソース或いはドレインに電
気的接続させて形成される。第３図に示す実施例
はフイールドプレート面上に更に絶縁膜８′を被
着し、該絶縁膜８′上に上記領域Ａをほぼ被う面
積に被覆導体１０4が設けられ、ソース電極６に
電気的接続されている。該被覆導体１０4はドレ
イン電極７側に電気的接続されても実施し得る。
また第４図はドレイン電極７に接続された配線１
１を更に延長させて領域Ａを充分被う形状に設
け、被覆導体１０5を配線と一体的に形成したも
のである。 In Figure 2a, the P - board 1 has the conventional
Similar to a MOSFET, a source region 2, a drain region 3, a P + channel region 4 and an N - high resistance layer 5 are formed, and a source electrode 6 is electrically connected to the source region 2, and a drain electrode 7 is electrically connected to the drain region 3. is,
The other substrate surfaces are covered with an insulating film 8.
Note that 9 is a gate electrode formed on a gate oxide film of a predetermined thickness provided on the channel region 4.
In order to eliminate the above-mentioned drawbacks of the conventional method, the field plate extending from the source electrode side and the field plate extending from the drain electrode side should not be extended too far from each other, and in addition, the area where the conductor is not covered, as shown in A in Fig. 1, should be avoided. In order to prevent this from occurring, both field plates are provided so as to partially overlap each other with an insulating layer in between near the center of the high-resistance layer region. That is, in the embodiment shown in FIG. 2a, a field plate 6' integrally provided with the source electrode is formed as a field plate extending from the source electrode side, and a covered conductor 1 is formed as a field plate extending from the drain electrode side.
0 1 is provided in the insulating layer close to the substrate surface with respect to the field plates 6' and 7', and is formed simultaneously using the process of creating the gate electrode 9, and is connected to the drain region 3. It is set up as an extension. Similarly, in Fig. 2 b and c, the coated conductor 1
0 2 and 10 3 are formed in the insulating film near the substrate surface, but they are not provided as extensions of the drain or source electrodes, but covered conductors 10 2 and 10 3 are formed in the form of islands covering region A. The coated conductor is connected to the source or drain field plate 6',
In the step of forming 7', it is electrically connected to the source or drain. In the embodiment shown in FIG. 3, an insulating film 8' is further deposited on the field plate surface, and a covered conductor 104 is provided on the insulating film 8' in an area that almost covers the area A. electrically connected to. The covered conductor 10 4 may be electrically connected to the drain electrode 7 side.
Also, FIG. 4 shows the wiring 1 connected to the drain electrode 7.
1 is further extended to sufficiently cover area A, and coated conductor 105 is formed integrally with the wiring.
第５図は本発明による被覆導体が設けられた高
耐圧MOSFETと被覆導体を具備していない前述
の従来MOSFETとの高温バイアス条件下におけ
るRONの時間的変化を示す。曲線は本発明によ
るMOSFETの、曲線は従来のMOSFETにお
ける変化を示し、図から明らかなように、従来
MOSFETは時間と共に急速に変化しているが本
発明MOSFETはほとんど変動せず安定した特性
を示す。尚試験時の温度は100℃、VDS＝200V及
びVGS＝OVである。 FIG. 5 shows the temporal change in R ON under high temperature bias conditions for a high voltage MOSFET provided with a coated conductor according to the present invention and the aforementioned conventional MOSFET not provided with a coated conductor. The curve shows the change in the MOSFET according to the present invention, and the curve shows the change in the conventional MOSFET.
Although MOSFETs change rapidly over time, the MOSFET of the present invention hardly changes and exhibits stable characteristics. The temperature during the test was 100°C, V DS = 200 V, and V GS = OV.
以上本発明によれば、ソース及びドレイン電極
と夫々一体的にフイールドプレートを形成するこ
とにより、ドレイン側のゲート電極端での電界集
中及びドレイン領域と高抵抗層との境界付近での
電界集中を緩和できる上、ドレイン電極と一体的
なフイールドプレートは、それにより覆われた高
抵抗層との間で蓄積層を発生させ、実質的に前記
フイールドプレートで覆われない高抵抗層より高
い不純物濃度領域と同等の動作を行わせることが
でき、高抵抗層に濃度勾配を形成したものと同等
の効果が得られ、電界集中が和らぐ。更に、被覆
導体の端部が上記両フイールドプレートと重なつ
ているため、高抵抗層領域上が導体で完全に被覆
されて外部電荷の影響を受けることが極めて少な
くなる。したがつて、特性変動のない信頼性のよ
い高耐圧MOSFETが得られる。 As described above, according to the present invention, by forming field plates integrally with the source and drain electrodes, electric field concentration at the end of the gate electrode on the drain side and near the boundary between the drain region and the high resistance layer can be reduced. In addition to being able to relax, the field plate integral with the drain electrode generates an accumulation layer between it and the high resistance layer covered by it, substantially resulting in a higher impurity concentration region than the high resistance layer not covered by said field plate. It is possible to perform the same operation as that of the high-resistance layer, and the same effect as that of forming a concentration gradient in the high-resistance layer can be obtained, and the electric field concentration is alleviated. Furthermore, since the ends of the covered conductor overlap with both of the field plates, the high-resistance layer region is completely covered with the conductor, so that it is extremely unlikely to be affected by external charges. Therefore, a highly reliable high voltage MOSFET with no characteristic fluctuations can be obtained.
第１図は従来装置の断面図、第２図ａは本発明
による高耐圧MOSFETの断面図、第２図ｂ，
ｃ、第３図、第４図は本発明による他の実施例の
高耐圧MOSFETの断面図、第５図は従来装置と
本発明による高耐圧MOSFETとのRONの特性を
比較した図である。
１：P-基板、２：ソース領域、３：ドレイン
領域、４：P+チヤネル領域、５：高抵抗層領域、
６：ソース電極、７：ドレイン電極、６′，７′：
フイールドプレート、８：絶縁膜、９：ゲート電
極、１０1，１０2：被覆導体。
Fig. 1 is a sectional view of a conventional device, Fig. 2a is a sectional view of a high voltage MOSFET according to the present invention, Fig. 2b,
c, Figures 3 and 4 are cross-sectional views of high voltage MOSFETs according to other embodiments of the present invention, and Figure 5 is a diagram comparing the R ON characteristics of a conventional device and a high voltage MOSFET according to the present invention. . 1: P - substrate, 2: source region, 3: drain region, 4: P + channel region, 5: high resistance layer region,
6: Source electrode, 7: Drain electrode, 6', 7':
Field plate, 8: Insulating film, 9: Gate electrode, 10 1 , 10 2 : Covered conductor.
Claims (1)
で、ドレイン領域と同一導電型の高抵抗領域が形
成された高耐圧MOS電界効果トランジスタにお
いて、 ソース領域から半導体基板の絶縁膜上に延びて
上記高抵抗領域の境界上を覆うフイールドプレー
トと、 ドレイン領域から半導体基板の絶縁膜上に延び
てドレイン領域と高抵抗領域との境界上を覆うフ
イールドプレートと、 上記両フイールドプレート間の絶縁膜を覆い、
且つ端部が絶縁層を介して上記両フイールドプレ
ートと重なり、一方のフイールドプレートに電気
的に接続された被覆導体とを備えてなり、該被覆
導体と絶縁膜上のフイールドプレートとで上記高
抵抗領域上の絶縁膜をほぼ被つてなることを特徴
とする高耐圧MOS電界効果トランジスタ。[Scope of Claims] 1. In a high-voltage MOS field effect transistor in which a high-resistance region of the same conductivity type as the drain region is formed surrounding a drain region formed on a semiconductor substrate, a source region is formed on an insulating film of a semiconductor substrate. a field plate extending from the drain region to cover the boundary of the high resistance region; a field plate extending from the drain region to the insulating film of the semiconductor substrate and covering the boundary between the drain region and the high resistance region; cover the insulating film,
and a coated conductor whose end portion overlaps both of the field plates through an insulating layer and is electrically connected to one of the field plates, and the coated conductor and the field plate on the insulating film have the high resistance. A high-voltage MOS field-effect transistor characterized by almost covering an insulating film on a region.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16069379A JPS5683077A (en) | 1979-12-10 | 1979-12-10 | High tension mos field-effect transistor |
| DE3046749A DE3046749C2 (en) | 1979-12-10 | 1980-12-10 | MOS transistor for high operating voltages |
| US06/655,638 US4614959A (en) | 1979-12-10 | 1984-09-28 | Improved high voltage MOS transistor with field plate layers for preventing reverse field plate effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16069379A JPS5683077A (en) | 1979-12-10 | 1979-12-10 | High tension mos field-effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5683077A JPS5683077A (en) | 1981-07-07 |
| JPS6350872B2 true JPS6350872B2 (en) | 1988-10-12 |
Family
ID=15720418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16069379A Granted JPS5683077A (en) | 1979-12-10 | 1979-12-10 | High tension mos field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5683077A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0460251B1 (en) * | 1990-06-05 | 1998-11-18 | Siemens Aktiengesellschaft | Method of fabricating a power-MISFET |
| US5918137A (en) * | 1998-04-27 | 1999-06-29 | Spectrian, Inc. | MOS transistor with shield coplanar with gate electrode |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53980A (en) * | 1977-07-13 | 1978-01-07 | Hitachi Ltd | Field-effect transistor of high dielectric strength |
-
1979
- 1979-12-10 JP JP16069379A patent/JPS5683077A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53980A (en) * | 1977-07-13 | 1978-01-07 | Hitachi Ltd | Field-effect transistor of high dielectric strength |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5683077A (en) | 1981-07-07 |
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