JPS622705B2 - - Google Patents
Info
- Publication number
- JPS622705B2 JPS622705B2 JP3770280A JP3770280A JPS622705B2 JP S622705 B2 JPS622705 B2 JP S622705B2 JP 3770280 A JP3770280 A JP 3770280A JP 3770280 A JP3770280 A JP 3770280A JP S622705 B2 JPS622705 B2 JP S622705B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- resistance layer
- drain
- source
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は高耐圧MOS電界効果半導体装置（以
下高耐圧MOSFETと略す）に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage MOS field effect semiconductor device (hereinafter abbreviated as high voltage MOSFET).
従来から知られている高耐圧MOSFETの断面
図を第１図に示す。同図において、１はＰ型半導
体基板で、該基板１にN+ソース領域２及びN+ド
レイン領域３が夫々形成されており、更にソース
領域２の周囲には自己整合プロセスによつて
MOSFETのゲートチヤネルのためのP+領域４が
設けられ、またP+領域４とN+ドレイン領域３間
の基板にはドレイン領域３に接続された同一導電
型の低不純物濃度層５（以下ピンチ抵抗層と呼
ぶ）が設けられている。上記のように不純物拡散
がなされた半導体基板に対して、該基板１の表面
にはN+ソース領域２に接続されたソース電極８
及びN+ドレイン領域３に接続されたドレイン電
極９が形成され、ドレイン電極９は先端が延長さ
れてフイールドプレート９′が設けられ、ドレイ
ン領域３に近接したN-ピンチ抵抗領域５の一部
がフイールドプレート９′で被われている。 Figure 1 shows a cross-sectional view of a conventionally known high voltage MOSFET. In the figure, 1 is a P-type semiconductor substrate, on which an N + source region 2 and an N + drain region 3 are formed, respectively, and the source region 2 is surrounded by a self-alignment process.
A P + region 4 for the gate channel of the MOSFET is provided, and a low impurity concentration layer 5 (hereinafter referred to as pinch) of the same conductivity type connected to the drain region 3 is provided in the substrate between the P + region 4 and the N + drain region 3 A resistive layer (referred to as a resistive layer) is provided. A source electrode 8 connected to an N + source region 2 is provided on the surface of the substrate 1 for a semiconductor substrate in which impurities have been diffused as described above.
and a drain electrode 9 connected to the N + drain region 3 is formed, the tip of the drain electrode 9 is extended to provide a field plate 9', and a part of the N - pinch resistance region 5 adjacent to the drain region 3 is formed. It is covered with a field plate 9'.
上記構造のMOSFETはゲート電極１０とフイ
ールドプレート９′の間に、絶縁膜１１で被覆は
されているが、Al或いは多結晶Siのような導体で
被覆されないピンチ抵抗層の領域５′が生じるこ
とになり、該導体被覆されないピンチ抵抗層の領
域５′は外部電荷の影響を受け易く、高温バイア
ス試験時等における動作時の耐圧（以下イオン耐
圧と呼ぶ）、ドレイン電流及びオン抵抗等の電気
的特性に変動を生じる欠点があつた。 Although the MOSFET having the above structure is covered with an insulating film 11 between the gate electrode 10 and the field plate 9', there is a pinch resistance layer region 5' that is not covered with a conductor such as Al or polycrystalline Si. The region 5' of the pinch resistance layer that is not coated with the conductor is easily affected by external charges, and the electrical characteristics such as withstand voltage (hereinafter referred to as ion withstand voltage), drain current, and on-resistance during operation during high-temperature bias tests etc. There was a drawback that the characteristics varied.
上記のような構造のMOSFETに対して、ピン
チ抵抗層の領域を絶縁膜を介して導体で完全に被
覆することも試みられているが、ピンチ抵抗層を
被う導体は電位的に浮いた状態か又はドレイン電
位、ソース電位等の特定の電位に固定されるもの
で、導体下にある半導体基板の表面状態にとつて
は必ずしも好ましいものではなかつた。 For MOSFETs with the above structure, attempts have been made to completely cover the pinch resistance layer region with a conductor via an insulating film, but the conductor covering the pinch resistance layer remains floating in potential. Alternatively, the conductor is fixed at a specific potential such as drain potential or source potential, which is not necessarily favorable for the surface condition of the semiconductor substrate underneath the conductor.
本発明は上記従来装置の欠点を除去し、信頼性
の高い高耐圧MOSFETを提供するもので、次に
実施例を挙げて本発明を詳細に説明する。 The present invention eliminates the drawbacks of the conventional device described above and provides a highly reliable high voltage MOSFET.The present invention will now be described in detail with reference to examples.
即ち、本発明は高耐圧MOSFETにおいて、ソ
ース領域及びドレイン領域間に位置する半導体基
板、特に低不純物濃度に形成されたN-ピンチ抵
抗層が外部電荷の影響を受けないように、半導体
基板面上を絶縁膜を介して外部の影響を受けない
材料で被覆するものである。 That is, the present invention provides a high breakdown voltage MOSFET in which a semiconductor substrate located between a source region and a drain region, particularly an N - pinch resistance layer formed with a low impurity concentration, is placed on the semiconductor substrate surface so that it is not affected by external charges. The material is coated with a material that is not affected by external influences via an insulating film.
第２図は本発明による一実施例のMOSFET半
導体装置の断面図を示し、従来装置と同様に不純
物拡散がなされた半導体基板１に於て、ピンチ抵
抗層５上の絶縁膜１１上に、ピンチ抵抗層５を完
全に被う形状に高抵抗層１４が設けられ、該高抵
抗層１４の一端１２はドレイン電極９に、他端１
３はソース電極８にオーミツク接続されている。
ここで上記高抵抗層１４は比較的高抵抗を示す材
料が選ばれ、多結晶Si或いは半絶縁材料が用いら
れる。高抵抗層１４の抵抗値が低い場合には、ド
レイン・ソース間電流が大きくなつて実用上半導
体装置としての機能が得られない惧れがあるた
め、ドレイン・ソース間電流が問題にならない程
度の抵抗値を示す高抵抗材料で形成される。上記
高抵抗層１４でピンチ抵抗層が被われた
MOSFETの各電極に夫々動作電圧及び入力信号
が供給されると、ソース電極及びドレイン電極間
に接続された高抵抗層の電圧勾配はほぼ一定にな
り、直下に位置するピンチ抵抗層５の電界を一定
に保つことができて外部電荷の影響を除去し、動
作の安定化を図ることができる。 FIG. 2 shows a cross-sectional view of a MOSFET semiconductor device according to an embodiment of the present invention. In a semiconductor substrate 1 in which impurities have been diffused similarly to the conventional device, a pinch resistance layer 5 is formed on an insulating film 11. A high resistance layer 14 is provided in a shape that completely covers the resistance layer 5, one end 12 of the high resistance layer 14 is connected to the drain electrode 9, and the other end 12 is connected to the drain electrode 9.
3 is ohmicly connected to the source electrode 8.
Here, a material exhibiting relatively high resistance is selected for the high resistance layer 14, and polycrystalline Si or a semi-insulating material is used. If the resistance value of the high-resistance layer 14 is low, the drain-source current will increase and there is a risk that it will not function as a practical semiconductor device. It is made of a high resistance material that exhibits a resistance value. A pinch resistance layer is covered with the high resistance layer 14.
When the operating voltage and input signal are supplied to each electrode of the MOSFET, the voltage gradient of the high resistance layer connected between the source electrode and the drain electrode becomes almost constant, and the electric field of the pinch resistance layer 5 located directly below becomes constant. Since it can be kept constant, the influence of external charges can be removed and operation can be stabilized.
上記高抵抗層１４はソース電極８にオーミツク
接続する代りにゲート電極１０に電気的接続して
も所期の目的を達成し得る。 The desired purpose can be achieved even if the high resistance layer 14 is electrically connected to the gate electrode 10 instead of being ohmicly connected to the source electrode 8.
上記高耐圧MOSFETにおいて、N+ドレイン領
域３に連結されたピンチ抵抗層５の他端側は、
P+チヤネル領域４と連結することなく適当な間
隔７が設定され、P-基板領域が残されている。
またソース領域２を囲んで形成されたチヤネル領
域４の外側基板表面にはP+不純物を注入したフ
イールドドープ領域６が形成されている。更にソ
ース領域２に電気的接続されたソース電極８は、
ソース領域２と同時にP+チヤネル領域４及びフ
イールドドープ領域６の一部にも電気的接続され
ている。このようにフイールドドープ領域６、チ
ヤネル領域４及びソース領域２を同時に電気的接
続すること、及び上記適当な間隔７を設けること
はいずれもMOSFETのカツトオフ耐圧及びオン
耐圧の向上に寄与する。 In the above high voltage MOSFET, the other end side of the pinch resistance layer 5 connected to the N + drain region 3 is
An appropriate spacing 7 is set without connecting the P + channel region 4, leaving a P − substrate region.
Further, a field doped region 6 into which P + impurities are implanted is formed on the outer substrate surface of the channel region 4 formed surrounding the source region 2 . Furthermore, the source electrode 8 electrically connected to the source region 2 is
The source region 2 is electrically connected to the P + channel region 4 and part of the field doped region 6 at the same time. Simultaneously electrically connecting the field doped region 6, channel region 4, and source region 2 in this way and providing the above-mentioned appropriate spacing 7 all contribute to improving the cut-off breakdown voltage and on-breakdown voltage of the MOSFET.
次に上記本発明による半導体装置の製造方法を
第３図ａ〜ｆを用いて説明する。 Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3a to 3f.
第３図ａにおいて、半導体基板１は低不純物濃
度のＰ型基板で、その表面にはソース領域及びチ
ヤネル領域となる部分をレジスト１６で被覆した
後表面を被つている薄い酸化膜１５を介して31P+
イオンがイオン注入される。注入された不純物は
更に熱処理が施こされて拡散され、N-ピンチ抵
抗層５が形成される。上記熱処理の過程で生成さ
れた厚い酸化膜１７は、第３図ｂに示す如く少な
くともチヤネル領域を形成する部分が写真食刻技
術を用いて一旦窓開けされ、続いて薄い酸化膜１
８が再び形成された状態で、レジスト１９を部分
的に残し、表面からイオン注入続いて拡散の処理
を施こしてチヤネル領域となるP+領域４がピン
チ抵抗層５の端から間隔７隔てた状態で形成され
る。その後拡散又はイオン注入を行なつてN+不
純物領域を形成し、ソース領域２及びドレイン領
域３を形成して表面を被つている酸化膜１７，１
８を除去する。酸化膜が除去された半導体基板
は、レジスト２０が部分的に塗布され、イオン注
入によつてフイールドドープ領域としてのP+領
域６が第３図ｃに示す如く形成される。 In FIG. 3a, the semiconductor substrate 1 is a P-type substrate with a low impurity concentration, and the surface thereof is coated with a resist 16 to form a source region and a channel region, and then a thin oxide film 15 covering the surface is formed. 31 P +
Ions are implanted. The implanted impurities are further diffused by heat treatment, and the N - pinch resistance layer 5 is formed. As shown in FIG. 3b, the thick oxide film 17 produced in the above heat treatment process is once opened using photolithography in at least the portion forming the channel region, and then the thin oxide film 17 is opened.
8 is formed again, the resist 19 is left partially, and ions are implanted from the surface, followed by diffusion to form a P + region 4, which will become a channel region, at a distance of 7 from the edge of the pinch resistance layer 5. formed in the state. After that, diffusion or ion implantation is performed to form an N + impurity region, and a source region 2 and a drain region 3 are formed, and oxide films 17 and 1 covering the surface are formed.
Remove 8. A resist 20 is partially applied to the semiconductor substrate from which the oxide film has been removed, and a P + region 6 as a field doped region is formed by ion implantation as shown in FIG. 3c.
上記のような工程を経て不純物拡散処理がなさ
れた半導体基板は、表面に気相成長法による厚い
酸化膜１１が形成され、ドレイン領域、ゲート領
域及びソース領域を被う厚い酸化膜は一旦除去さ
れた後再び薄い酸化膜２１が形成される。次に高
抵抗層１４及びゲート電極１０のための多結晶Si
層が形成され、被着された多結晶Si層はイオン注
入等で所望の抵抗値に制御された後エツチングに
よつて不要部分が除去されゲート電極１０、高抵
抗層１４が形成される。該高抵抗層１４は続いて
第３図ｄに示す如く後述するAlとオーミツク接
続するための端部１２，１３が拡散法又はイオン
注入法で低抵抗処理される。高抵抗層が形成され
た基板１は全面にリンシリケートガラス膜２２が
被着され、ソース領域、ドレイン領域、後述する
ソース電極と上記低抵抗部１３を電気的接続する
ためのコンタクト窓が夫々第３図ｅに示す如く開
孔される。窓開けされた半導体基板面にAl蒸着
が施こされ、所望のパターンにエツチングされて
ソース電極８、ドレイン電極９が形成され、同時
に高抵抗層１４の一端１２及び他端１３がソース
電極８及びドレイン電極９に電気的接続される。
最後に保護膜２３で半導体基板上が被われて第３
図ｆに示す如く高耐圧MOSFETを完成する。 The semiconductor substrate that has been subjected to impurity diffusion treatment through the steps described above has a thick oxide film 11 formed on its surface by vapor phase growth, and the thick oxide film covering the drain region, gate region, and source region is once removed. After that, a thin oxide film 21 is formed again. Next, polycrystalline Si for the high resistance layer 14 and the gate electrode 10 is
After the deposited polycrystalline Si layer is controlled to a desired resistance value by ion implantation or the like, unnecessary portions are removed by etching to form the gate electrode 10 and the high resistance layer 14. Subsequently, as shown in FIG. 3d, the ends 12 and 13 of the high resistance layer 14 for ohmic connection with Al, which will be described later, are treated to have a low resistance by a diffusion method or an ion implantation method. A phosphosilicate glass film 22 is deposited on the entire surface of the substrate 1 on which a high resistance layer is formed, and a contact window for electrically connecting a source region, a drain region, and a source electrode to be described later with the low resistance section 13 is formed in each of the substrates 1. The holes are drilled as shown in Figure 3e. Al vapor deposition is performed on the surface of the semiconductor substrate with the window opened, and etched into a desired pattern to form the source electrode 8 and the drain electrode 9. At the same time, one end 12 and the other end 13 of the high resistance layer 14 are connected to the source electrode 8 and the drain electrode 9. It is electrically connected to the drain electrode 9.
Finally, the top of the semiconductor substrate is covered with a protective film 23.
A high voltage MOSFET is completed as shown in Figure f.
以上本発明によれば、外部電荷の影響を受け易
いピンチ抵抗層上が完全に導体又は半導体材料で
被われ、電位的にも中間的なレベルに固定される
ため特性変化が極めて少なく、信頼性の高い装置
を得ることができる。またピンチ抵抗層を被う膜
として高抵抗層が用いられ、且つ高抵抗層の端部
はドレイン電極及びソース電極又はゲート電極に
電気的接続されているため、高抵抗層の電圧勾配
が一定になり、その直下にあるピンチ抵抗層領域
の電界も一定に近づけることができてオン状態の
耐圧の向上を図り、高耐圧素子の耐圧改善の理想
とされているピンチ抵抗領域の電圧勾配一定、つ
まり電界を一定の状態に近づけることができ、す
ぐれた耐圧特性を得ることができる。 As described above, according to the present invention, the pinch resistance layer, which is susceptible to the influence of external charges, is completely covered with a conductor or semiconductor material and the potential is fixed at an intermediate level, resulting in extremely little change in characteristics and reliability. You can get high quality equipment. In addition, since a high resistance layer is used as a film covering the pinch resistance layer, and the ends of the high resistance layer are electrically connected to the drain electrode and the source electrode or gate electrode, the voltage gradient of the high resistance layer is constant. This makes it possible to make the electric field in the pinch resistance layer region directly below a constant value, thereby improving the withstand voltage in the on state. The electric field can be kept close to a constant state, and excellent withstand voltage characteristics can be obtained.
実施例してドレイン領域とチヤネル領域間に低
不純物濃度のピンチ抵抗層を設けたMOSFETを
挙げて本発明を説明したが、ピンチ抵抗層が形成
されていないMOSFET、チヤネルのためのP+領
域が形成されていないMOSFET、或いはピンチ
抵抗層及びP+領域共に形成されていない
MOSFETにおいても同様に本発明を実施するこ
とができ、素子の信頼性及び動作の安定化を図る
ことができる。 The present invention has been explained using a MOSFET in which a pinch resistance layer with a low impurity concentration is provided between the drain region and the channel region as an example. MOSFET not formed, or both pinch resistance layer and P + region not formed
The present invention can be similarly implemented in MOSFETs, and the reliability and operation of the device can be stabilized.
第１図は従来装置の断面図、第２図は本発明に
よる一実施例の断面図、第３図ａ〜ｆは同実施例
の製造工程を説明するための断面図である。
１：P-基板、２：ソース領域、３：ドレイン
領域、５：N-ピンチ抵抗層、８：ソース電極、
９：ドレイン電極、１０：ゲート電極、１２，１
３：接続用低抵抗層。１４：高抵抗層。
FIG. 1 is a sectional view of a conventional device, FIG. 2 is a sectional view of an embodiment of the present invention, and FIGS. 3 a to 3f are sectional views for explaining the manufacturing process of the same embodiment. 1: P -substrate , 2: source region, 3: drain region, 5: N -pinch resistance layer, 8: source electrode,
9: drain electrode, 10: gate electrode, 12,1
3: Low resistance layer for connection. 14: High resistance layer.
Claims (1)
型のドレイン領域及びソース領域が形成された
MOS電界効果半導体装置において、チヤネル領
域上に、絶縁膜を介してドレイン電極とソース電
極又はゲート電極に電気的接続された高抵抗層を
形成し、高抵抗層でチヤネル領域上を被つてなる
ことを特徴とする高耐圧NOS電界効果半導体装
置。1 A drain region and a source region of a second conductivity type are formed on a semiconductor substrate having a first conductivity type.
In a MOS field effect semiconductor device, a high resistance layer electrically connected to the drain electrode and the source electrode or the gate electrode via an insulating film is formed on the channel region, and the high resistance layer covers the channel region. A high-voltage NOS field-effect semiconductor device featuring:
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3770280A JPS56133870A (en) | 1980-03-22 | 1980-03-22 | Mos field effect semiconductor device with high breakdown voltage |
| US07/277,440 US4947232A (en) | 1980-03-22 | 1988-11-28 | High voltage MOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3770280A JPS56133870A (en) | 1980-03-22 | 1980-03-22 | Mos field effect semiconductor device with high breakdown voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56133870A JPS56133870A (en) | 1981-10-20 |
| JPS622705B2 true JPS622705B2 (en) | 1987-01-21 |
Family
ID=12504852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3770280A Granted JPS56133870A (en) | 1980-03-22 | 1980-03-22 | Mos field effect semiconductor device with high breakdown voltage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56133870A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0618251B2 (en) * | 1983-02-23 | 1994-03-09 | 株式会社東芝 | Semiconductor device |
| US5374843A (en) * | 1991-05-06 | 1994-12-20 | Silinconix, Inc. | Lightly-doped drain MOSFET with improved breakdown characteristics |
| JPH0788141A (en) * | 1993-06-30 | 1995-04-04 | San Beam:Kk | Rotary chair |
-
1980
- 1980-03-22 JP JP3770280A patent/JPS56133870A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56133870A (en) | 1981-10-20 |
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