JP2000164854A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a low threshold and high dielectric strength. SOLUTION: A semiconductor device comprises a first conductive-type semiconductor wafer 1 having an impurity concentration of a first prescribed concentration, a first second conductive-type semiconductive region 2, having an impurity concentration of the second prescribed concentration or lower and formed on one main surface of the semiconductor wafer 1, a second second conductive-type semiconductive region 3, having an impurity concentration higher than the second prescribed concentration and formed on one main surface of the semiconductor wafer 1, a third semiconductor region 4 having an impurity concentration higher than the second prescribed concentration and formed in the second semiconductor region 3, a channel region 7 formed between the first semiconductor region 2 and the second semiconductor region 3 so as to have its conductive type varied, a gate electrode 8 applied by voltage for changing the conductive type of the channel region 7, and a gate insulation film 9 for insulating the gate electrode 8 from the semiconductor wafer 1. The channel region 7 is constituted with surface concentration higher than that of the first prescribed concentration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral insulated gate field effect semiconductor device.

[0002]

2. Description of the Related Art As this kind of semiconductor device, there is one shown in FIG. These are provided along a main surface of a semiconductor substrate A of a first conductivity type having an impurity concentration of a first predetermined concentration and a semiconductor substrate A having an impurity concentration of a second predetermined concentration. A first semiconductor region B of a second conductivity type,
A second conductive type second semiconductor region C provided along one main surface of the semiconductor substrate A with an impurity concentration higher than the second predetermined concentration; A third semiconductor region D having a high impurity concentration and provided inside the second semiconductor region C along one main surface of the semiconductor substrate A.
A channel region E whose conductivity type can change between the first semiconductor region B and the second semiconductor region C; a gate electrode F to which a voltage is applied so as to change the conductivity type of the channel region E; A gate insulating film G for insulating between the gate electrode F and the semiconductor substrate A side.

More specifically, a region between the first and second semiconductor substrate regions B and C on the semiconductor substrate A is a channel region E. In this semiconductor device, when the surface concentration of the channel region E is lowered by lowering the impurity concentration of the semiconductor substrate A, the threshold voltage is lowered.

Further, the first semiconductor region B is
The second semiconductor region C 1 is called a drain region, and the third semiconductor region D 2 is called a source region.

[0005]

In the above-mentioned conventional semiconductor device, the concentration of the first semiconductor region B is set to a first predetermined concentration, and the second semiconductor region having a higher concentration than the first predetermined concentration is used. By making the concentration lower than that in the region C 2, the withstand voltage between the drain region and the source region can be increased.

However, when the surface concentration of the channel region E is reduced in order to lower the threshold voltage, the depletion layer extending from the drift region toward the source region is kept in contact with the source region. When the depletion layer comes into contact with the source region as described above, the withstand voltage is reduced, and a phenomenon called so-called punch-through occurs.

On the other hand, if the channel region E is made longer by providing a gap between the first and second semiconductor regions B and C so as to prevent the occurrence of punch-through, the channel resistance increases and the on-resistance increases. I will.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device having a low threshold voltage and a high withstand voltage, and a method of manufacturing the same.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device of a first conductivity type having a first predetermined impurity concentration, and a second conductive type semiconductor substrate having a first predetermined impurity concentration. A first semiconductor region of a second conductivity type provided on one main surface side of the semiconductor substrate and having an impurity concentration equal to or lower than a predetermined concentration;
A second semiconductor region of a second conductivity type provided along one main surface of the semiconductor substrate and having an impurity concentration higher than a predetermined concentration, and an impurity having a higher concentration than the second predetermined concentration. A third semiconductor region having a concentration and provided inside the second semiconductor region along one main surface of the semiconductor substrate; and a third semiconductor region located between the first semiconductor region and the second semiconductor region. A channel region whose conductivity type can be changed, a gate electrode to which a voltage is applied so as to change the conductivity type of the channel region, and insulation between the gate electrode and the semiconductor substrate including the first semiconductor region and the channel region And a gate insulating film, wherein the channel region has a surface concentration higher than a first predetermined concentration.

According to a second aspect of the present invention, in the first aspect of the present invention, the first semiconductor region is polymerized on both the gate electrode and the gate insulating film with the channel region interposed therebetween. Having an area,
The overlapping region has a structure in which the impurity concentration is relatively low inside the first semiconductor region.

According to a third aspect of the present invention, in the second aspect of the present invention, the first semiconductor region has an adjacent region adjacent to the overlap region along one principal surface of the semiconductor substrate, The gate insulating film includes an adjacent region insulating portion that insulates the gate electrode from an adjacent region of the first semiconductor region, and a channel region insulating portion that insulates the gate electrode from the channel region. The region insulating portion is configured to be thicker than the channel region insulating portion.

According to the manufacturing method of the invention described in claim 4,
A semiconductor substrate of a first conductivity type having an impurity concentration of a first predetermined concentration, and a second conductivity type provided on one main surface side of the semiconductor substrate having an impurity concentration of a second predetermined concentration or less. First
A second conductive type second semiconductor region having an impurity concentration higher than the second predetermined concentration and provided along one main surface of the semiconductor substrate; A third semiconductor region having an impurity concentration higher than the concentration and provided inside the second semiconductor region along one main surface of the semiconductor substrate; a first semiconductor region and a second semiconductor region A channel region located between the channel region and the conductivity type, a gate electrode to which a voltage is applied to change the conductivity type of the channel region, a semiconductor substrate including the gate electrode, the first semiconductor region, and the channel region A gate insulating film that insulates between the gate electrode and the gate electrode. The channel region has a surface concentration lower than a first predetermined concentration, and the first semiconductor region includes the gate electrode and the gate electrode. Heavy on any of the gate insulating films A polymerization region having a relatively low impurity concentration inside the first semiconductor region, and the first semiconductor region extending along one principal surface of the semiconductor substrate. And the gate insulating film has an adjacent region insulating portion that insulates the gate electrode from the adjacent region of the first semiconductor region, and the gate electrode and the channel region. A method of manufacturing a semiconductor device for manufacturing a semiconductor device having a channel region insulating portion to be insulated, wherein the adjacent region insulating portion is thicker than the channel region insulating portion. Forming a first semiconductor region, forming an insulating layer serving as the gate insulating film on the semiconductor substrate including the first semiconductor region,
An opening is formed in the insulating layer including a portion where the first semiconductor region overlaps, an impurity of a second conductivity type is injected through the opening to form the channel region, and the channel region is formed including the channel region. An insulating layer serving as the gate insulating film is formed again on a semiconductor substrate, and the gate electrode is formed along the insulating layer.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.

Reference numeral 1 denotes a semiconductor substrate having a first conductivity type (P type).
And the impurity concentration is the first predetermined concentration. This semiconductor substrate 1 is provided with a first semiconductor region 2 of a second conductivity type (N type) having an impurity concentration of a second predetermined concentration along one main surface thereof, and a second predetermined region. A second conductive type second semiconductor region 3 having an impurity concentration higher than the concentration is provided. A third semiconductor region 4 having an impurity concentration higher than a second predetermined concentration is provided along the main surface of the semiconductor substrate 1 inside the first semiconductor region 2. .

Incidentally, the first semiconductor region 2 is called a drift region. Further, as described above, the second semiconductor region 3 is the first semiconductor region of the second conductivity type (N type).
2, which is a source region electrically short-circuited to the semiconductor substrate 1 of the first conductivity type (P type). The third semiconductor region 4 is a drain region.

Reference numeral 5 denotes a source electrode, which is a second source region.
To the semiconductor region 3. Reference numeral 6 denotes a drain electrode which is connected to the third semiconductor region 4 which is a drain region. A channel region 7 is located between the first semiconductor region 2 and the second semiconductor region 3 and has a different conductivity type. The channel region 7 has a surface density higher than the first predetermined density.

Reference numeral 8 denotes a gate electrode to which a voltage is applied so as to change the conductivity type of the channel region 7. The gate electrode 8 is insulated from the semiconductor substrate 1 side including the first semiconductor region 2 and the channel region 7 by a gate insulating film 9 provided on one main surface of the semiconductor substrate 1.
An intermediate insulating film 10 insulates between the source electrode 5 and the drain electrode 6.

In such a semiconductor device, in order to lower the threshold value, even if the first predetermined concentration of the semiconductor substrate 1 is lowered, a channel whose surface concentration is higher than the first predetermined concentration. In the region 7, since the depletion layer extending from the first semiconductor region 2 to the second semiconductor region 3 hardly spreads only at the surface portion, punch-through hardly occurs and the breakdown voltage does not decrease.

By setting the impurity concentration of the semiconductor substrate 1 and the surface concentration of the channel region 7 to different values,
Any threshold can be set.

Next, a second embodiment of the present invention will be described below with reference to FIG. Note that portions having substantially the same functions as those of the first embodiment are denoted by the same reference numerals, and only the differences from the first embodiment will be described. This embodiment is basically the same as the first embodiment, except that the first semiconductor region 2 has a region with a relatively low impurity concentration inside.

More specifically, the first semiconductor region 2 includes a gate electrode 8 and a gate insulating film with a channel region 7 interposed therebetween.
9 has a polymerization region 11 for polymerization. The overlapping region 11 has a relatively low impurity concentration inside the first semiconductor region 2.

In such a semiconductor device, in addition to the effect of the first embodiment, in the overlapping region 11 in the first semiconductor region 2, the impurity concentration in the first semiconductor region 2 is relatively low. Therefore, the depletion layer easily spreads toward the third semiconductor region 4 from the interface between the semiconductor substrate 1 and the first semiconductor region 2 which are in contact with each other immediately below the gate electrode 8, and the breakdown voltage can be increased.

Next, a third embodiment of the present invention will be described below with reference to FIGS. Parts having substantially the same functions as in the second embodiment are denoted by the same reference numerals,
Only different points from the second embodiment will be described. In this embodiment,
Basically the same as the second embodiment, except that the gate insulating film
9 has a thick portion and a thin portion, and the thick portion and the thin portion insulate the gate electrode 8 from the semiconductor substrate 1 including the first semiconductor region 2 and the channel region 7. Is different.

More specifically, the first semiconductor region 2 is formed in an adjacent region adjacent to the overlap region 11 along one main surface of the semiconductor substrate 1.
Has 12 In addition, the gate insulating film 9 is
8 and an adjacent region insulating portion 9a for insulating the adjacent region 12 of the first semiconductor region 2 and a channel region insulating portion 9b for insulating the gate electrode 8 and the channel region 7 from each other. Is thicker than the channel region insulating portion 9b.

Next, referring to FIGS. 4 (a) to 4 (e), the manufacturing procedure of the device will be described below. First, as shown in FIG. 1A, an insulating film 20 serving as a gate insulating film 9 is formed along one main surface of a semiconductor substrate 1 of a first conductivity type (P type).

Thereafter, a first opening (not shown) is formed in the insulating film, and a second conductivity type (N-type) impurity is implanted and diffused through the first opening. A first semiconductor region along one main surface of the semiconductor substrate 1
2 is formed, and an insulating layer 20 serving as a gate insulating film 9 is formed again on the semiconductor substrate 1 including the first semiconductor region 2 as shown in FIG. Note that the thickness of the insulating layer 20 formed in the portion where the first opening is formed is smaller than the thickness of the insulating layer 20 formed in the portion where the first opening is not formed.

Thereafter, as shown in FIG. 2C, a second opening 30a is formed in the thin insulating film 20 described above.
The third opening 30 is formed in the thick insulating film 20 over the thin insulating film 20.
b is formed, and impurities of the first conductivity type (P type) are implanted through the third opening 30b as shown by arrows, and a channel region 7 is formed along one main surface of the semiconductor substrate 1. Form.

After that, an insulating layer 20 to be a gate insulating film 9 is formed again on the semiconductor substrate 1 including the channel region 7, and then the gate is formed along the insulating layer 20 as shown in FIG. The electrode 8 is formed in a step shape, and further, a source region which is the second semiconductor region 3 of the second conductivity type (N type) and a second
And a drain region which is a third semiconductor region 4 of the conductivity type (N type).

Finally, an insulating film 20 serving as the intermediate insulating film 10 is formed on the semiconductor substrate 1, and further, contact holes 40 for connecting metal electrodes are formed at two places. 40 A drain electrode 6 and a source electrode 5 are formed.

In this semiconductor device, in addition to the effects of the second embodiment, the gate electrode 9 is formed of the adjacent region insulating portion of the gate insulating film 9 which is thicker than the channel region insulating portion 9b.
9a insulates the first semiconductor region 2 from the first semiconductor region 2, so that the electric field spreads in a direction along one main surface of the semiconductor substrate 1, and the electric field intensity in the first semiconductor region 2 is reduced. The withstand voltage can be further increased.

Further, according to the above-described manufacturing method, the insulating layer 20 formed on the channel region 7 and serving as the channel region insulating portion 9b is formed on the portion where the third opening 30c is formed once. Since it is the layer 20, it is thinner than the insulating layer 20 that becomes the adjacent region insulating portion 9a that insulates between the adjacent region 12 adjacent to the overlapping region 11 and the gate electrode 9, and the adjacent region insulating portion 9a becomes 9b, the interface between the adjacent region insulating portion 9a and the channel region insulating portion 9a and the boundary surface between the channel region 9 can be seen from the direction orthogonal to one main surface of the semiconductor substrate 1. The electric field spreads in a direction along one main surface of the semiconductor substrate 1, and the electric field intensity in the first semiconductor region 2 is reduced, so that the effect that the withstand voltage can be further increased can be ensured. Can be played.

In the first to third embodiments, the first conductivity type is P-type and the second conductivity type is N-type, but the first conductivity type is N-type and the second conductivity type is N-type. The same effect can be obtained even if the conductivity type is P-type.

[0033]

According to the first aspect of the present invention, the surface concentration is higher than the first predetermined concentration even if the first predetermined concentration of the semiconductor substrate is reduced in order to lower the threshold value. In the channel region, the depletion layer extending from the first semiconductor region to the second semiconductor region is difficult to expand only in the surface portion, so that punch-through hardly occurs and the breakdown voltage does not decrease.

According to a second aspect of the present invention, in addition to the effect of the first aspect of the present invention, the overlapped region in the first semiconductor region has a relatively low impurity concentration inside the first semiconductor region. Therefore, the depletion layer easily spreads from the interface between the semiconductor substrate and the first semiconductor region, which are in contact with each other immediately below the insulated gate, toward the third semiconductor region, and the breakdown voltage can be increased.

According to a third aspect of the present invention, in addition to the effect of the second aspect of the present invention, the gate electrode is formed in the first semiconductor region by the adjacent region insulating portion of the gate insulating film which is thicker than the channel region insulating portion. Are insulated from each other, the electric field spreads in a direction along one main surface of the semiconductor substrate, the electric field intensity in the first semiconductor region is reduced, and the withstand voltage can be further increased.

According to the manufacturing method of the fourth aspect,
Since the insulating layer formed on the channel region and serving as the channel region insulating portion is an insulating layer formed again in the portion where the opening is formed once, the insulating layer between the adjacent region adjacent to the overlapping region and the gate electrode is formed. It is thinner than the insulating layer serving as the adjacent region insulating portion to be insulated, and the adjacent region insulating portion can be surely made thicker than the channel region insulating portion. The interface between the region insulating portion and the channel region insulating portion and the boundary surface of the channel region can be aligned, and the electric field spreads in a direction along one main surface of the semiconductor substrate, so that the electric field in the first semiconductor region can be increased. The strength can be reduced, and the effect that the withstand voltage can be further increased can be reliably achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view of a second embodiment of the present invention.

FIG. 3 is a sectional view of a third embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing procedure of the above.

FIG. 5 is a sectional view of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 first semiconductor region 3 second semiconductor region 4 third semiconductor region 7 channel region 8 gate electrode 9 gate insulating film 9a adjacent region insulating portion 9b channel region insulating portion 10 overlapping region 11 adjacent region

Claims (4)

[Claims] A semiconductor substrate of a first conductivity type having an impurity concentration of a first predetermined concentration, and a semiconductor substrate having an impurity concentration of a second predetermined concentration or less are provided on one main surface side of the semiconductor substrate. Second
And a second conductive type second semiconductor region having an impurity concentration higher than the second predetermined concentration and provided along one main surface of the semiconductor substrate. And the second
A third semiconductor region having an impurity concentration higher than a predetermined concentration and provided inside the second semiconductor region along one main surface of the semiconductor substrate; a first semiconductor region and a second semiconductor region; A channel region located between the semiconductor region and having a variable conductivity type, a gate electrode to which a voltage is applied to change the conductivity type of the channel region, a gate electrode, the first semiconductor region, and the channel region; A semiconductor device comprising: a gate insulating film that insulates a channel region from a semiconductor substrate; wherein the channel region has a surface concentration higher than a first predetermined concentration. 2. The semiconductor device according to claim 1, wherein the first semiconductor region has a polymerized region that is polymerized on both the gate electrode and the gate insulating film with the channel region interposed therebetween. 2. The semiconductor region according to claim 1, wherein the impurity concentration is relatively low inside the first semiconductor region. 3. The semiconductor device according to claim 1, wherein the first semiconductor region has an adjacent region adjacent to the overlap region along one main surface of the semiconductor substrate, and the gate insulating film includes the gate electrode and the first semiconductor. It has an adjacent region insulating portion insulating the adjacent region of the region and a channel region insulating portion insulating the gate electrode and the channel region,
2. The semiconductor device according to claim 1, wherein the adjacent region insulating portion is thicker than the channel region insulating portion. 4. A semiconductor substrate of a first conductivity type having an impurity concentration of a first predetermined concentration, and provided on one main surface side of the semiconductor substrate having an impurity concentration of a second predetermined concentration or less. Second
And a second conductive type second semiconductor region having an impurity concentration higher than the second predetermined concentration and provided along one main surface of the semiconductor substrate. And the second
A third semiconductor region having an impurity concentration higher than a predetermined concentration and provided inside the second semiconductor region along one main surface of the semiconductor substrate; a first semiconductor region and a second semiconductor region; A channel region located between the semiconductor region and having a variable conductivity type, a gate electrode to which a voltage is applied to change the conductivity type of the channel region, a gate electrode, the first semiconductor region, and the channel region; A gate insulating film that insulates the channel region from the semiconductor substrate side, wherein the channel region has a surface concentration lower than a first predetermined concentration, and the first semiconductor region includes the gate electrode. And a polymerization region that polymerizes in both of the gate insulating films, the polymerization region has a relatively low impurity concentration inside the first semiconductor region, and the first semiconductor region And said An adjacent region that is adjacent to the overlap region along one main surface of the conductive substrate, the gate insulating film is an adjacent region insulating unit that insulates the gate electrode from an adjacent region of the first semiconductor region, and A method of manufacturing a semiconductor device, comprising: a channel region insulating portion that insulates a gate electrode from the channel region, wherein the adjacent region insulating portion manufactures a semiconductor device that is thicker than the channel region insulating portion. Forming the first semiconductor region along one main surface of the first semiconductor region; forming an insulating layer serving as the gate insulating film on the semiconductor substrate including the first semiconductor region; An opening is formed in the insulating layer including the superposed portion of the second region, an impurity of the second conductivity type is injected through the opening to form the channel region, and the half including the channel region is formed. The method of manufacturing a semiconductor device body on a substrate serving as the gate insulating film an insulating layer is formed again, and forming the gate electrode along the insulating layer.