JPS6349842U

JPS6349842U -

Info

Publication number: JPS6349842U
Application number: JP13391987U
Authority: JP
Priority date: 1987-09-03
Filing date: 1987-09-03
Publication date: 1988-04-04

Description

[Brief explanation of the drawing]

第１図は従来の同期装置のブロツク図、第２図
及び第３図は第１図の装置のタイムチヤート、第
４図は本考案の一実施例のブロツク図、第５図及
び第６図は第４図の実施例のタイムチヤートであ
る。４０……親装置、４２……端末装置、４４，４
６，５４，５６，５８……伝送路、４８……カウ
ンタ、５０，５２，６２，６４，６６，６８……
Ｄ型フリツプフロツプ、６０……シフトレジスタ
。 Fig. 1 is a block diagram of a conventional synchronizing device, Figs. 2 and 3 are time charts of the device shown in Fig. 1, Fig. 4 is a block diagram of an embodiment of the present invention, and Figs. 5 and 6. is a time chart of the embodiment shown in FIG. 40... Parent device, 42... Terminal device, 44,4
6, 54, 56, 58...Transmission line, 48...Counter, 50, 52, 62, 64, 66, 68...
D-type flip-flop, 60...shift register.

Claims

[Claims for Utility Model Registration] A serial data synchronization device including a lower-level device 42, a higher-level device 40, and a transmission path connecting these, wherein the lower-level device 42 is connected to the higher-level device 40 via the transmission path. a counting means 48 receiving a data synchronization clock for specifying the phase of the serial data and a first clock synchronized with each bit of the serial data; a second clock synchronized with the first clock and a plurality of bits of the serial data; A first flip-flop 52 receives the serial data to be transmitted, and a second flip-flop 50 receives the first clock and the serial data to be transmitted. Receives data via the transmission path, and from the higher-level device 40 to the lower-level device 42
A shift register 60 receives at its clock terminal the first clock sent back via A serial data synchronizer comprising a group of flip-flops 62, 64, 66, 68 which perform parallel conversion and whose outputs are sampled by the clock of the host device 40.