JPS6343774B2 - - Google Patents

Info

Publication number
JPS6343774B2
JPS6343774B2 JP57152034A JP15203482A JPS6343774B2 JP S6343774 B2 JPS6343774 B2 JP S6343774B2 JP 57152034 A JP57152034 A JP 57152034A JP 15203482 A JP15203482 A JP 15203482A JP S6343774 B2 JPS6343774 B2 JP S6343774B2
Authority
JP
Japan
Prior art keywords
buffer memory
buffer
match
data
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57152034A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5942686A (ja
Inventor
Hideki Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57152034A priority Critical patent/JPS5942686A/ja
Publication of JPS5942686A publication Critical patent/JPS5942686A/ja
Publication of JPS6343774B2 publication Critical patent/JPS6343774B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57152034A 1982-08-31 1982-08-31 情報処理装置 Granted JPS5942686A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57152034A JPS5942686A (ja) 1982-08-31 1982-08-31 情報処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57152034A JPS5942686A (ja) 1982-08-31 1982-08-31 情報処理装置

Publications (2)

Publication Number Publication Date
JPS5942686A JPS5942686A (ja) 1984-03-09
JPS6343774B2 true JPS6343774B2 (no) 1988-09-01

Family

ID=15531603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57152034A Granted JPS5942686A (ja) 1982-08-31 1982-08-31 情報処理装置

Country Status (1)

Country Link
JP (1) JPS5942686A (no)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6266348A (ja) * 1985-09-18 1987-03-25 Nec Corp キヤツシユメモリ制御装置におけるストアチエツク方式
JPS63173146A (ja) * 1987-01-13 1988-07-16 Yokogawa Electric Corp キヤツシユメモリ制御システム
US4804581A (en) * 1987-05-14 1989-02-14 Ppg Industries, Inc. Chip resistant coatings
JPH03288245A (ja) * 1990-04-03 1991-12-18 Mitsubishi Electric Corp データ処理装置
JP2636088B2 (ja) * 1991-03-15 1997-07-30 甲府日本電気株式会社 情報処理装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5324260A (en) * 1976-08-19 1978-03-06 Matsushita Electric Works Ltd Open circuit delayed non-contact relay

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5324260A (en) * 1976-08-19 1978-03-06 Matsushita Electric Works Ltd Open circuit delayed non-contact relay

Also Published As

Publication number Publication date
JPS5942686A (ja) 1984-03-09

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