JPS6342530Y2 - - Google Patents

Info

Publication number
JPS6342530Y2
JPS6342530Y2 JP2078579U JP2078579U JPS6342530Y2 JP S6342530 Y2 JPS6342530 Y2 JP S6342530Y2 JP 2078579 U JP2078579 U JP 2078579U JP 2078579 U JP2078579 U JP 2078579U JP S6342530 Y2 JPS6342530 Y2 JP S6342530Y2
Authority
JP
Japan
Prior art keywords
circuit board
stem
integrated circuit
hybrid integrated
metal stem
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2078579U
Other languages
English (en)
Japanese (ja)
Other versions
JPS55122349U (enrdf_load_stackoverflow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2078579U priority Critical patent/JPS6342530Y2/ja
Publication of JPS55122349U publication Critical patent/JPS55122349U/ja
Application granted granted Critical
Publication of JPS6342530Y2 publication Critical patent/JPS6342530Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Die Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)
JP2078579U 1979-02-20 1979-02-20 Expired JPS6342530Y2 (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2078579U JPS6342530Y2 (enrdf_load_stackoverflow) 1979-02-20 1979-02-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2078579U JPS6342530Y2 (enrdf_load_stackoverflow) 1979-02-20 1979-02-20

Publications (2)

Publication Number Publication Date
JPS55122349U JPS55122349U (enrdf_load_stackoverflow) 1980-08-30
JPS6342530Y2 true JPS6342530Y2 (enrdf_load_stackoverflow) 1988-11-08

Family

ID=28852416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2078579U Expired JPS6342530Y2 (enrdf_load_stackoverflow) 1979-02-20 1979-02-20

Country Status (1)

Country Link
JP (1) JPS6342530Y2 (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS55122349U (enrdf_load_stackoverflow) 1980-08-30

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