JPS6339694U - - Google Patents
Info
- Publication number
- JPS6339694U JPS6339694U JP13256286U JP13256286U JPS6339694U JP S6339694 U JPS6339694 U JP S6339694U JP 13256286 U JP13256286 U JP 13256286U JP 13256286 U JP13256286 U JP 13256286U JP S6339694 U JPS6339694 U JP S6339694U
- Authority
- JP
- Japan
- Prior art keywords
- pair
- terminals
- circuit
- signal
- alarm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Electromechanical Clocks (AREA)
Description
第1図は本考案回路の一実施例の回路構成図、
第2図は第1図示の回路各部の信号波形図である
。
10……発振回路、11……分周回路、12…
…1/2分周回路、13……インバータ、15a
〜18a,15b〜18b……オア回路、15c
〜18c……アンド回路、19……ナンド回路、
20……ステツプモータ、22……イクスクル―
シブオア回路、23……ノア回路、24……スピ
ーカ、Q1〜Q6……FET,SW……スイツチ
、A,B……端子。
FIG. 1 is a circuit configuration diagram of an embodiment of the circuit of the present invention.
FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 10... Oscillation circuit, 11... Frequency dividing circuit, 12...
...1/2 frequency divider circuit, 13... Inverter, 15a
~18a, 15b ~18b...OR circuit, 15c
~18c...AND circuit, 19...NAND circuit,
20...Step motor, 22...Excl.
Shibu-OR circuit, 23...NOR circuit, 24...Speaker, Q1 to Q6 ...FET, SW...Switch, A, B...terminal.
Claims (1)
駆動信号を外付けのステツプモータに供給し、該
ステツプモータの回転で指針を駆動する半導体集
積回路化されたアナログ時計回路において、 該指針が所定位置となつたとき閉成する外付け
のスイツチにより該一対の端子のうちの一方の端
子が所定レベルとされたとき、該駆動信号が出力
されてない期間にトリガ信号を生成するトリガ回
路と、 該トリガ信号を供給されて互いに同相のアラー
ム信号を生成するアラーム回路と、 該駆動信号が出力されてない期間に該アラーム
信号を該一対の端子より出力する出力回路とを設
けてなり、 該一対の端子に外付けされた発音装置で互いに
同相のアラーム信号を取り出して発音を行なうよ
う構成してなるアナログ時計回路。[Claims for Utility Model Registration] A semiconductor-integrated analog device that supplies drive signals of mutually opposite phases from a pair of terminals at regular time intervals to an external step motor, and drives a pointer by the rotation of the step motor. In a clock circuit, when one terminal of the pair of terminals is set to a predetermined level by an external switch that closes when the pointer reaches a predetermined position, a trigger is generated during a period when the drive signal is not output. a trigger circuit that generates a signal; an alarm circuit that is supplied with the trigger signal and generates alarm signals in phase with each other; and an output circuit that outputs the alarm signal from the pair of terminals during a period when the drive signal is not output. An analog clock circuit is provided with a pair of terminals, and is configured to extract alarm signals having the same phase with each other and generate sound using a sound generating device externally attached to the pair of terminals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13256286U JPH045037Y2 (en) | 1986-08-29 | 1986-08-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13256286U JPH045037Y2 (en) | 1986-08-29 | 1986-08-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6339694U true JPS6339694U (en) | 1988-03-15 |
JPH045037Y2 JPH045037Y2 (en) | 1992-02-13 |
Family
ID=31032066
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13256286U Expired JPH045037Y2 (en) | 1986-08-29 | 1986-08-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH045037Y2 (en) |
-
1986
- 1986-08-29 JP JP13256286U patent/JPH045037Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPH045037Y2 (en) | 1992-02-13 |
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