JPH0438315Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an integrated circuit for an electronic watch having an alarm function and the like.

[Conventional technology]

Nowadays, electronic clocks using crystal oscillators are highly accurate and have become extremely popular.

The circuit of this electronic watch consists of an oscillation circuit that is combined with a crystal resonator, a frequency divider circuit that divides the reference frequency signal from the oscillation circuit, a waveform shaping circuit that adjusts the waveform of the divided reference frequency signal, and a motor that drives the circuit. The drive circuit for this purpose is an integrated circuit (hereinafter simply referred to as IC).
The crystal oscillator, various operation switches, and clock motors such as step motors are externally attached to the IC.

Incidentally, many of today's electronic watches have additional functions such as alarm functions and other timer functions, and watch ICs perform not only the oscillation circuit, frequency dividing circuit, waveform shaping circuit, and drive circuit, but also alarm functions, etc. It is an IC that integrates many logic circuits such as AND circuits and OR circuits, and external sounding bodies such as piezoelectric buzzers and speakers are also attached.

By the way, in this IC-based clock circuit,
After attaching the crystal resonator externally, it is necessary to make a final adjustment to the oscillation frequency of the oscillation circuit that is combined with the crystal resonator, and this final adjustment is usually performed by attaching the crystal resonator externally to the clock circuit IC. This is done after all external parts such as various switches, motors, sounding elements, etc. I C
(for example, Japanese Patent Application Laid-open No. 104566/1983).

[Problem that the invention attempts to solve]

As mentioned above, providing an external terminal exclusively for rate monitoring is a major obstacle in miniaturizing the IC.
When circuits for additional functions such as alarm functions are added, it is important to reduce the number of external terminals even by one in order to miniaturize the IC.

For this reason, it is possible to use the alarm signal output terminal connected to the sounding body to make the alarm signal a rate monitor signal, but the rate adjustment of the oscillation circuit is usually completed by connecting all parts to the IC. Since the alarm signal is used as a rate monitor signal, the alarm sound is emitted from the sounding body,
The drawback was that adjustments had to be made in a noisy environment.

[Means to solve the problem]

The present invention provides an integrated circuit for a watch with an alarm function that outputs an alarm signal of opposite phase from an alarm signal output terminal, such as applying an opposite phase signal to both poles of a sounding body. When a specific voltage is applied to the alarm input terminal, a rate monitor signal of the same phase can be continuously output from the alarm signal output terminal.

[Effect]

The IC according to the present invention outputs the rate monitor signal from the alarm signal output terminal, and in order to output the rate monitor signal, a specific voltage is applied to the alarm input terminal, so an external terminal of the IC is added. There is no need to do this, and the rate monitor signal is 2
Since the in-phase signal is outputted from the alarm signal output terminals, the alarm sound is not emitted when adjusting the rate of the oscillation circuit without activating the sounding body.

〔Example〕

As an embodiment of the present invention, an integrated circuit for a watch to which only an alarm function is added will be described below.

As shown in FIG. 1, this IC has a basic circuit 12 consisting of an oscillation circuit 14, a frequency divider circuit 16, a waveform shaping circuit 18, and a drive circuit 20 in the IC 10, and the frequency divider circuit 16 generates a standard audio frequency ₁ . a frequency signal;
₂ reference frequency signals and ₃ reference frequency signals as modulation signals are extracted, and the ₁ signal output terminal,
_{The 2-} signal output terminal and _{the 3-} signal output terminal are connected to the input terminal of the 3-input type first AND circuit 22 of the alarm signal generation circuit 30. In addition to the first AND circuit 22, this alarm signal generation circuit 30 is composed of a two-input type second AND circuit 24, a third AND circuit 26, and a first inverter 28, and has an output terminal of the first AND circuit 22. is connected to the input terminal of the second AND circuit 24 and also connected to the input terminal of the third AND circuit 26 via the first inverter 28, and the output terminal of the second AND circuit 24 is connected to the first OR circuit 42 and the sounding body 56. The output terminal of the third AND circuit 26 is connected to the first alarm signal output terminal 50 through the first buffer circuit 46 as a driver of a piezoelectric buzzer, and the output terminal of the third AND circuit 26 is connected to the first alarm signal output terminal 50 through the second OR circuit 44 and the second buffer circuit 48. and is connected to the second alarm signal output terminal 52.

The alarm input terminal 32 is connected to each input terminal of the second AND circuit 24 and the third AND circuit 26 in the alarm signal generation circuit 30 via a second inverter 34 constituting an alarm circuit, The output terminal is connected to the input terminal of the fourth AND circuit 38 via the third inverter 36 of the rate adjustment mode detection circuit 40, and the other input terminal of the fourth AND circuit 38 is connected to the input terminal of the fourth AND circuit 38 that constitutes the alarm circuit. 2 so that the alarm operation signal which is the output of the inverter 34 is a negative input.
The output terminal of the fourth AND circuit 38 is connected to the output terminal of the inverter 34, and the output terminal of the fourth AND circuit 38 is connected to each input terminal of the first OR circuit 42 and the second OR circuit 44 via a fifth AND circuit 54 forming a gate circuit. The other input terminal of the fifth AND circuit 54 is connected to _one reference signal terminal of the frequency dividing circuit 16.

The second inverter 34 constituting the alarm circuit and the third inverter 36 in the rate adjustment mode detection circuit 40 have different threshold levels, and the threshold level of the third inverter 36 is set to the threshold level of the second inverter 34. Set it higher than the threshold level.

For the IC 10 configured as described above, a rate adjusting member 60 such as a trimmer capacitor and a crystal oscillator 5 are provided.
8 is connected to the reference frequency signal input terminal so as to be combined with the oscillation circuit 14, and the watch motor 62 is connected to the drive signal output terminal from the drive circuit 20.
The alarm input terminal is connected to the + power supply via a resistor 64 and grounded via a reference switch 66 and a sound stop switch 68, and is further connected to the first alarm signal output terminal 50 and the second alarm signal output terminal 52. A sounding body 56 such as a piezoelectric buzzer is connected.

The operation of the circuit in the IC 10 to which various external components such as the crystal oscillator 58 and the motor 62 are attached in this manner will be described below.

The oscillation circuit 14 oscillates a reference signal with a high and stable frequency by combining with a crystal oscillator 58 that vibrates at an accurate specific frequency, and the rate adjustment member 60 oscillates the oscillation circuit 14.
The oscillation frequency of the oscillation circuit 14 can be finely adjusted, and the stable reference frequency signal oscillated from the oscillation circuit 14 is converted into a reference signal ₃ having a frequency of, for example, 1 Hz by the frequency dividing circuit 16, and the reference signal ₃ is passed through the waveform shaping circuit. The signal is shaped in step 18 to be used as a timing signal for driving a motor, and is used as a driving signal via a driving circuit 20 to rotate a clock motor such as a step motor.

Also, the frequency dividing circuit outputs an audible frequency reference signal.
₁ and the reference signal ₂ for modulation, for example, an 8 Hz reference signal and the 1 Hz reference signal ₃ in the first AND circuit 22 in the alarm signal generation circuit 30.
Since the input terminal of the first AND circuit 22 is connected so as to send the signal to the signal A, the output signal of the first AND circuit 22, shown as signal A in FIG. After a gap of 2 seconds, the audio frequency signal is repeated 4 times in 0.5 seconds.

The input terminal of the second inverter 34 constituting the alarm circuit is connected to the resistor 64 when the reference switch 66 or the stop switch 68 is open.
, the input terminal of the second inverter 34, that is, the alarm input terminal 32.
An H level signal is applied to the second
The C signal which is the output of the inverter 34 becomes L level and does not output an alarm operation signal. Therefore, the second AND circuit 2 in the alarm signal generation circuit 30
4 and the third AND circuit 26 are closed,
When the ring stop switch 68 is set and the reference switch 66 is turned on at a predetermined time, the alarm input terminal 32 is grounded via the reference switch 66 and the ring stop switch 68.
The voltage at the alarm input terminal 32 is inverted to the L level, which is the ground level, as shown as the B signal in FIG.
The signal becomes H level and an alarm operation signal is output. By outputting the H level signal as the C signal as the alarm operation signal, the second AND circuit 2 in the alarm signal generation circuit 30
4 and the third AND circuit 26 are opened.

Therefore, the second AND circuit 24 passes the A signal which is the output of the first AND circuit 22, and outputs the first alarm signal shown as the F signal in FIG. 1 AND circuit 2 inverted by inverter 28
The A signal which is the output of 2 will be passed,
A second alarm signal, shown as the G signal in FIG. 2, is output. This first alarm signal is transmitted to the first OR circuit 4.
2, is amplified by the first buffer circuit 46, and the first
A second alarm signal, which is applied to the sounding body 56 from the alarm signal output terminal 50 and whose phase is opposite to that of the first alarm signal, also passes through the second OR circuit 44 and is amplified by the second buffer circuit 48 to produce a second alarm signal. It is applied to the sounding body 56 from the output terminal 52.

By setting the first alarm signal and the second alarm signal in opposite phases in this manner, a voltage approximately twice the output voltage of each of the first buffer circuit 46 and the second buffer circuit 48 is applied to the sounding element 56. A notification sound can be generated at a predetermined time.

As mentioned above, when an L level signal is applied to the alarm input terminal 32 and an H level alarm operation signal is output to the C signal which is the output signal of the second inverter 34 forming the alarm circuit, the rate adjustment is performed. Since the fourth AND circuit 38 in the mode detection circuit 40 receives the alarm operation signal as a negative input, the E signal, which is the output signal of the fourth AND circuit 38, is at the L level, so the rate adjustment mode signal is not output. Also, the guide switch 66 or the stop switch 68 is opened, and the alarm input terminal 32 is opened.
Since the D signal, which is the output signal of the third inverter 36, is at the L level even when the H level signal is applied to the inverter, the E signal, which is the output signal of the fourth AND circuit 38, is maintained at the L level. .

By the way, when finely adjusting the oscillation frequency of the oscillation circuit 14 combined with the crystal oscillator 58 by adjusting the rate adjustment member 60, the alarm input terminal 32
When connected to ground through the adjustment resistor 70, the alarm input terminal 32 is voltage-divided by the resistor 64 whose one end is connected to the + power supply and the adjustment resistor 70 whose one end is grounded. A specific intermediate potential will be applied.

As described above, since the threshold level of the third inverter 36 is set higher than the threshold level of the second inverter 34, the intermediate potential of the alarm input terminal 32 is set to be higher than that of the second inverter 34. If the potential is between the threshold level and the threshold level of the third inverter 36, the C signal, which is the output signal of the second inverter 34 constituting the alarm circuit, is maintained at the L level, but the rate adjustment mode The D signal, which is the output signal of the third inverter 36 in the detection circuit 40, is inverted to H level, and the fourth AND circuit 38 uses the D signal as an input signal and the C signal as a negative input.
A rate adjustment mode signal of H level is output as the output signal E signal. Therefore, by inputting the H level rate adjustment mode signal to the fifth AND circuit 54 which uses the E signal as an input signal, the fifth AND circuit 54 is opened, and the fifth AND circuit 54 constituting the gate circuit A rate monitor signal based on the reference signal ₁ is outputted as the output H signal so as to pass the reference signal ₁ from the frequency dividing circuit 16,
The rate monitor signal is sent to the first OR circuit 42 and the first
It is output to the first alarm signal output terminal 50 via the buffer circuit 46, and the second OR circuit 44
It is also output to the second alarm signal output terminal 52 via the second buffer circuit 48.

In this way, by setting the potential of the alarm input terminal 32 to a specific intermediate potential, the reference signal ₁ is outputted as a rate monitor signal to the first alarm signal output terminal 50 and the second alarm signal output terminal 52. However, since the voltages output to both output terminals at this time are common mode voltages, the sounding element 5
Even if the reference signal ₁ is an audible frequency signal, the sounding body 56 does not produce any notification sound.

Note that the reference signal that is the basis of the rate monitor signal is not limited to the case where it is common to _{the one} reference signal that is the basis of the alarm signal, but it may be any suitable frequency that is suitable for measuring the oscillation frequency of the oscillation circuit 14. The input terminal of the fifth AND circuit 54 and the frequency divider circuit 1 are connected so that the reference signal of the fifth AND circuit 54 is extracted from the frequency divider circuit 16 and inputted to the fifth AND circuit 54 constituting the gate circuit.
Needless to say, the reference signal output terminal 6 can be connected to the appropriate reference signal output terminal.

[Effect of idea]

As mentioned above, the IC according to the present invention only when a specific intermediate potential is applied to the alarm input terminal.
Since the rate monitor signal of the same phase is output to the first alarm signal output terminal and the second alarm signal output terminal, the oscillation frequency of the oscillation circuit can be adjusted by using the first alarm signal output terminal or the second alarm signal output terminal. There is no need for an external terminal dedicated to the rate monitor, and it is easy to miniaturize the IC. Since the rate monitor signal outputted to the second alarm signal output terminal is in the same phase, even if a sounding element is connected to the alarm signal output terminal, the sounding element is not driven, and therefore the user can enjoy a calm environment without being bothered by noise. Able to perform adjustment work in a controlled environment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an assembled watch integrated circuit according to the present invention, and FIG. 2 is a time chart. 10... integrated circuit, 12... basic circuit, 14...
... Oscillation circuit, 16 ... Frequency dividing circuit, 18 ... Waveform shaping circuit, 20 ... Drive circuit, 22 ... First AND circuit, 24 ... Second AND circuit, 26 ... Third AND circuit, 28 ... ...First inverter, 30... Alarm signal generation circuit, 32... Alarm input terminal, 34... Second inverter, 36... Third inverter, 38... Fourth AND circuit, 40... Rate adjustment mode detection Circuit, 42...First OR circuit, 4
4...Second OR circuit, 46...First buffer circuit, 48...Second buffer circuit, 50...First alarm signal output terminal, 52...Second alarm signal output terminal, 54...First buffer circuit 5 AND circuit, 56...
...Sounding body, 58...Crystal oscillator, 60...Rate adjustment member, 62...Motor, 64...Resistor, 66
...Guideline switch, 68...Sound stop switch,
70...Adjustment resistor.

Claims (1)

[Claims for Utility Model Registration] An oscillator circuit that generates a reference signal of a frequency corresponding to the operating state of a rate adjusting member, a frequency divider circuit that divides the frequency of the reference signal, and an output signal from the frequency divider circuit. a waveform shaping circuit that outputs a timing signal with a predetermined cycle; a drive circuit that receives the timing signal and outputs a drive signal that drives the watch motor; An alarm input terminal to which a high potential H level signal or a low potential L level signal on the ground side is input, a first alarm signal output terminal to which a terminal of a sounding body for alarm sound notification is connected, respectively; The potential applied to the second alarm signal output terminal and the alarm input terminal is
an alarm circuit that detects a reversal from a preset L level or H level and outputs an alarm operation signal; and a first alarm signal for alarm sound notification in response to the alarm operation signal; an alarm signal generation circuit that outputs a second alarm signal of opposite phase; a first buffer circuit that receives the first alarm signal, amplifies the signal, and outputs the amplified signal to the first alarm signal output terminal; a second buffer circuit that receives a second alarm signal, amplifies the signal, and outputs the signal to the second alarm signal output terminal;
a rate adjustment mode detection circuit that detects application of a specific potential intermediate between the level potential and outputs a rate adjustment mode signal; and inputs a reference frequency signal from the frequency dividing circuit to one input terminal. a gate circuit that outputs a rate monitor signal based on the reference frequency signal when the rate adjustment mode signal is input to another input terminal; and a first alarm signal from the alarm signal generation circuit and the gate circuit. a first OR circuit which inputs a rate monitor signal from the gate circuit and supplies both signals to the first buffer circuit, and inputs a second alarm signal from the alarm signal generation circuit and a rate monitor signal from the gate circuit. and a second OR circuit that supplies both signals to the second buffer circuit.