JPS5857120B2 - Clock buzzer drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a watch buzzer drive circuit that utilizes a frequency division stage output.

Conventionally, in clock buzzer drive circuits that utilize frequency divider stage outputs, the combination of outputs from the frequency divider stage is fixed, so the input waveform to the buzzer is always constant, and the drive circuit also has a constant output. In order to make the volume variable, methods such as using a volume or switching a low resistance value were used.

However, this method has disadvantages in that it is not suitable for miniaturization because the volume and the resistor become large in size, and it is also uneconomical.

The present invention aims to eliminate the above-mentioned drawbacks and to perform volume adjustment in a compact and economical manner by electrically switching circuits.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and reference numeral O8C is an oscillation circuit in which a piezoelectric material such as crystal or lithium tantalate is used for oscillation.

F-Fl・・・・・・F-Fn is flip
It is a flop and constitutes the frequency dividing circuit 11.

1 and 2 are NAND circuits, 3 is a NOR circuit, 4 is a buffer circuit, SP is a buzzer, Swl is a switch, A is a control input terminal, a - i indicates input/output terminal symbols for explaining FIG. 2, VDD indicates the 7/high level side of the power supply, and ssc indicates the low level side terminal of the power supply.

Here, the output of the oscillation circuit O8C is the flip-flop F
-F1 to F-Fn are connected in series to a first-stage flip-flop F-Fl of a frequency divider circuit 11.

Further, one of the inputs of the NAND circuit 10 is connected to the output of the flip-flop F-Fr of the frequency divider circuit 11, and the other side is connected to the VDD or VSS side of the power source by the switch Sw1. teeth,
Flip-flop F-Fr.

The output of F-Fm and the output of NAND circuit 1 are connected, and the output of NAND circuit 2 and a control input for controlling this output are connected to NOR circuit 3, and the buzzer SP is connected via buffer circuit 4. connected to be supplied to the

To explain the case where the watch buzzer circuit according to the present invention is operated in the above configuration, the oscillation circuit O8
In C, for example, oscillation is performed by a piezoelectric oscillator such as crystal or lithium talate, and the frequency divider circuit 11 generates an appropriate frequency, that is, in a clock circuit, an IHz output is obtained from the flip-flop F-Fn. The frequency is further divided to provide an output to a clock circuit (not shown).

Now, when switch SW1 is set to connect to the VSS side of the power supply, a digital waveform as shown in Figure 2a is input to input a, but regardless of this, the NA
The output of the ND circuit 1 remains at level 5.

By the way, since the waveforms shown in Figure 2 d and e are input to the inputs d and e of the NAND circuit 2, the NAND
As shown in FIG. 2f, the output of the D circuit 2 is the waveform of the input d separated by the waveform of the input e.

Therefore, when the input terminal A of the NOR circuit 30 becomes low level due to a sound generation instruction from a sound generation instruction circuit (not shown),
Since the OR circuit 3 is equivalent to an inverter related only to the input f, the output waveform is transmitted and the current is amplified by the buffer circuit 4 to drive the buzzer SP to generate sound. However, when there is no instruction to generate sound, the input terminal A Since the signal is at bi-level, the output of the NOR circuit 3 is always at a low level, and therefore no drive waveform is provided to the buzzer SP via the buffer circuit 4, and the sound generation is stopped.

Here, in the case of a watch, the buzzer SP which is the sounding body has its resonance point almost aligned with the repetition frequency of the rectangular wave of the input d, the switch Sw1 is connected to the VSS side of the power supply, and the input is input from the input terminal A. When a low level input is supplied to g, the waveform of input d is intermittent with the waveform of human input e as described above (front part of Fig. 2 i), and in this case, both h and i The waveform has a duty ratio of 1:1.

Therefore, the buzzer SP whose resonance point is aligned with the repetition frequency of the rectangular wave of the input d is supplied with an input signal whose fundamental wave component is maximized, and the volume is maximized.

Next, let us consider the case where the switch Sw1 is connected to the VDD side of the power supply.

Since VDD is bi-level, NAND circuit 1 is manually operated.
The output C is obtained as shown in the second half of the time chart of FIG. 2, and the second half waveform of the output f is obtained by the NAND circuit 2.

Thereafter, a signal is supplied to the buzzer SP in the same way as when the switch Sw1 is connected to the VSS side of the power supply.

By the way, when the switch S'w1 is connected to the VDD side of the power supply, the ratio of the time when the voltage is applied to the buzzer SP and the time when the voltage is not applied is approximately 1:3 when the input e reaches the noise level.

Therefore, the fundamental wave component supplied to the buzzer SP decreases, and the noise level also decreases, so the volume decreases compared to when the duty ratio was 1:1.

As described above, according to the present invention, the volume of the buzzer can be changed digitally by changing the duty ratio of the buzzer drive pulse through a combination of the frequency dividing stage outputs of the frequency dividing circuit 110. Since the volume can be changed without the need for external parts such as a volumetric volume or a resistor, it has the excellent effect of providing a compact and economical buzzer drive circuit for watches.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a timepiece buzzer drive circuit according to the present invention, and FIG. 2 is a diagram showing a time chart of a first timing section. O8C...Oscillation circuit, F-F1~F'-Fn・
...Flip-flop, 1,2...NA
ND circuit, 3...NOR circuit, 4...
Buffer circuit, SP...buzzer, swl...
...Switch, 11... Frequency divider circuit, VDD
tvsS...Power supply, A...Input terminal.

Claims (1)

[Claims] 1. In a circuit that drives a buzzer using the output from the frequency dividing stage of an oscillation circuit, the pulse duty ratio can be changed and the volume can be adjusted by changing the combination of the frequency dividing stage outputs. Buzzer drive circuit for watches.