JPS60191520A - Clock pulse generating device - Google Patents

Abstract

PURPOSE:To correct the frequency in both leading and lagging directions by subtracting a clock pulse of a frequency division stage of a frequency divider and adding the clock pulse to other frequency division output. CONSTITUTION:The frequency divider 2 frequency-divides sequentially the output of an oscillator 1. A clock pulse subtractor 3 subtract a clock pulse of a frequency division stage in the frequency divider 2 at a prescribed rate based on the timing of a timing setting section 4. Further, a clock pulse adder 5 adds the clock pulse variably the frequency division stage of the frequency divider 2 within the summing time adjusted by a control section 6. When the rate of the addition is larger than the rate of subtraction, the frequency is adjusted in the leading direction and when small, the frequency is adjusted in the lag direction. Thus, the frequency is corrected in both the leading and lagging direction.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generator suitable for use in electronic watches.

Conventionally, clock pulses in electronic clocks, frequency dividers, etc.
Frequency adjustment is performed by changing the oscillation frequency in an oscillator. For example, in an oscillator using a crystal oscillator, the frequency is adjusted by changing the capacitance of a capacitor in the case where a filter is constructed together with the crystal oscillator.

However, in this case, the capacitor must be attached externally, the crystal oscillator must be matched with the capacitor, or the trimmer must be trimmed using a trimmer capacitor +j, which complicates the watch assembly process. Due to the need for storage space for the capacitor, etc.
There were problems such as hindering the miniaturization of watches. Furthermore, the range of frequencies that could be modulated was narrow depending on the capacitance of the capacitor, and only crystal oscillators with extremely limited resonant frequencies could be used.

The present invention was made in view of the above-mentioned circumstances, and the frequency is determined by subtracting the clock signal of the frequency division stage consisting of the frequency division device provided at the rear stage of the oscillator, and adding the clock pulse to the other frequency division output. By performing correction, we provide a clock pulse generation circuit that can be manufactured easily and miniaturized, has a wide frequency correction range, can easily perform frequency correction, and can obtain a highly accurate clock signal. This is what I am trying to do.

An embodiment of the present invention will be described below with reference to all the drawings. 1st
The figure is a block diagram showing its configuration. The oscillator l uses all crystal oscillators, and the frequency is, for example, 32.768 K.
Oscillates a Hz signal.

In the frequency dividing device 2, the output of the oscillator 1 is successively frequency-divided by, for example, a multi-stage connected flip-flop circuit. The clock pulse subtracter 3 subtracts the clock pulses of the frequency dividing stages in the gap-N frequency divider 2 from the timing of the timing setting section 4 at a constant rate. The timing setting section 4 generates pulses from the output of the branching device 2 to provide the subtraction timing of the subtracter 3 and the addition timing of the adder 5. to make. The addition Hals control section 6 controls the Hals addition ratio in the adder 5 by external adjustment input.

The clock pulse adder 5 variably adds the clock pulses of the frequency dividing stages of the frequency dividing device 2 within the addition time adjusted by the control unit 6.

When this addition ratio is larger than the subtraction ratio, it can be adjusted in the forward direction, and when it is smaller, it can be adjusted in the delay direction.

FIG. 2 is a detailed circuit diagram of oscillator l of FIG. 1. In the figure, 11 is a crystal resonator, and 12 and 13 are its terminal inputs. Reference numeral 14 denotes an oscillation stage amplifier having an inverter function, which is provided between terminals 12 and 13 via an output resistor 15. This amplifier 14 is realized, for example, by an inverter using a complementary MO8. 16 is a feedback resistor provided between the input and output terminals of the amplifier 14. In this case, this resistor 16 is connected to an N-channel MO8 type FET 17 and a P-channel MO8 type FET.
J s are connected in parallel, and the DC power supplies VDb and V
81i f: Realized by applying an awn to the dart. 19 and 20 are capacitors that are provided at the input and output ends of the crystal resonator 11 and constitute a filter together with the resonator 1. 7-19 and 20 are built into the integrated circuit 2 together with the amplifier 14 and resistors 15 and 16.

FIG. 3 is an example of a circuit embodying the conceptual diagram shown in FIG. That is, the frequency transmitted from oscillator 1 is 32.768 K.
Hz output is T-type flip-flop circuit 3, 3-bit T-type flip-flop, V2, T-type flip-flop 70
Nof 3s, 3(.

35, 36, and subsequent frequency dividing stages 37'5f: Normally, the frequency is sequentially divided at the frequencies shown in the figure.

OR circuit 38, AND circuit 39, T type flip frog with set 40, NAND type SR flip frog 47. The AND circuit 42 constitutes a pulse subtraction system. The AND circuits 43 and 44, the OR circuit 45, the AND circuit 46, the NAND type SR flip 70 and 47, the AND OR circuit 48, the resistors 49 to 52, and the trimmer terminals T and -T4 constitute a pulse addition system. AND circuits 53, 54, inverter 55,
Shift register C example, t H D W free lag frog 1
pit] 56 constitutes a timing setting system for pulse subtraction and addition. It is assumed that each of the T-type flip-flops performs a rising operation.

FIG. 4 is a timing chart showing operation waveforms of each part in FIG. 3, and the operation of the circuit in FIG. 3 will be explained below with reference to this diagram as appropriate. That is, the output a of the AND circuit 43 normally has a frequency of 16.384 KHz;
When the output from the AND circuit 44 is at a high level, the output from the AND circuit 44 is added to the frequency division system through the OR circuit 45. The frequency of the output d of the free-lag frog 34 is 512H2, but the output e of the free-lag frog 4Q is higher.

During the bell, the input d of the OR circuit 38 is inhibited, and the subtracted output f is supplied to the 7-lip-frog 35.

The input value to the shift register 56 is a pulse from the frequency dividing stage 37, which is a rising nozzle having a pulse width of 1/128 seconds that is synchronized with the rise of the 64 Hz signal of the frequency dividing stage once every 30 seconds, for example. The output J of the shift register 56 operates in synchronization with the read pulse h (φW). This output ki
l''i flip-flop 41.and dart 42 results in a one-shot rising pulse with a width of 172,048 seconds,
Frigg Fronk 40'f: Set. The output e of the flip flora f 4o is set and then the next 512H
The output is high level until the rising edge of the 2nd signal.

As described above, the input d of the OR circuit 38 is prohibited at this time. The rate of delay due to this is 51 in 30 seconds.
Since input of one 2 Hz signal is prohibited, □ Ki 65PPM 12X30.

On the other hand, when all the external trimmer terminals are at a low level, the output m of the AND/OR circuit 48 is always at a low level, and the output n of the AND circuit 46 is also always at a low level. Therefore, at this time, the input C of the OR circuit 45 is always at a low level, and its output C cannot be added. As a result, the oscillation frequency is delayed by -65 PPM.

Also, if only the trimmer terminal T is set to high level,
The output of the AND/OR circuit 48 is 1024f (Z signal is supplied to that extent, but at the time of addition 7, the frequency is doubled, so the output n of the AND circuit 46 is 204f at the time of addition.
It is at a high level only during one vertical period of 8H2. During this time, four rising pulses are supplied to the flip 70 knob 32 through the entire OR circuit 45. i.e. 16 in 30 seconds
．． Since 4 pulses can be added to the 384 KHz input, 8 PPM 16384 x 30 times will be added in □. Therefore, when combined with the above-mentioned subtraction, the result is a subtraction (delay) of approximately 8-65=-57 PPM.

In this way, 2'=16 additions or subtractions can be performed by combining the inputs of the trimmer terminals T'1 to T. The most pulse addition is performed in %T'1 to 1.
゛4 is all at a high level, and at this time, the amount of addition is high, and when combined with the subtraction, it is about 1l22-65
=57PP will be added. The table below shows the ratio of addition (advance) and subtraction (delay) depending on the combination of the inputs of the trimmer terminal.Actually, this value may differ slightly depending on the feedback of addition and subtraction, or it may be different. The effect is usually of truncated order.

0...Low level...Local level In this embodiment, the oscillation frequency can be corrected from -65 PPM to +57 PPM at intervals of '18PP]V1. It can be arbitrarily set by changing the way the input pulses are conveyed to the circuit 48, increasing or decreasing the number of trimmer terminals, etc. In the embodiment, the subtraction ratio is constant and the addition ratio is variable to adjust the frequency, or this method is reversed, and the addition ratio is constant and the subtraction ratio is variable. It goes without saying that the same effects can be obtained by making variable.

As explained above, the present invention has the following advantages. That is, since the clock pulse of the frequency dividing stage of the frequency dividing device is subtracted and other clock pulses are added, it is possible to advance the frequency and correct the delay in either direction. Also, since there is no need to adjust the frequency of the oscillator, there is no need to fine-tune the capacitor length as in the past, there is no need to consider matching between the crystal resonator and the capacitor, and there is no need to use a trimmer capacitor. Frequency scrutiny improves. Furthermore, since there is no increase in input/output connections due to tuning, oscillation characteristics such as oscillation starting voltage are not adversely affected. Furthermore, since the oscillator does not require much precision from the capacitor, the capacitor can be built into the integrated circuit, which greatly contributes to simplifying the assembly process of electronic watches and making the watches more compact. In addition, the frequency range to be corrected can be set arbitrarily if it is widened, and a crystal oscillator with a relatively wide range of resonance frequencies can be used, which simplifies the manufacturing of crystal oscillators. Cost reduction can be expected. Furthermore, since the human power for the timing setting section that controls the adders and subtracters is extracted from the branch unit, there is no need to separately provide a pulse generator, and the circuit configuration is not complicated.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a circuit diagram of its oscillator, Figure 3 is a detailed diagram of Figure 1, and Figure 4 is a timing waveform diagram for explaining its operation. It is. 1... Oscillator, 2... Frequency divider, 3... Subtractor,
4...timing setting section, 5...adder, 6...
Addition pulse control section, 1...Crystal oscillator, 1
4...Amplifier, I6...ft°pack resistor,!
9゜20... Capacitor. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (1)

[Claims] An oscillator that obtains a constant period signal, a division device that divides the output of this oscillator, a subtractor that reduces the number of clock pulses at the frequency division stage constituted by this frequency division device, and a frequency divided σ by the frequency division device. Another chronocouparnu number 'f: an adder capable of increasing the number of digits; a timing setting section which takes the output of the frequency dividing device as input and provides the subtraction timing of the subtracter and the addition timing of the adder; The oscillator includes a crystal oscillator, an oscillation stage amplifier having an inverter function connected to both ends thereof, and a feedback circuit provided between the input and output terminals of the oscillator. The oscillation stage amplifier, the feedback resistor, and the pair of capacitors are built into an integrated circuit, and the oscillation stage amplifier, the feedback resistor, and the pair of capacitors are built into an integrated circuit. A clock pulse generator characterized by: