JPS6338863B2 - - Google Patents
Info
- Publication number
- JPS6338863B2 JPS6338863B2 JP55179443A JP17944380A JPS6338863B2 JP S6338863 B2 JPS6338863 B2 JP S6338863B2 JP 55179443 A JP55179443 A JP 55179443A JP 17944380 A JP17944380 A JP 17944380A JP S6338863 B2 JPS6338863 B2 JP S6338863B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- nitride film
- polycrystalline silicon
- selective oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- 230000003647 oxidation Effects 0.000 claims description 26
- 238000007254 oxidation reaction Methods 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 230000001590 oxidative effect Effects 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 230000007261 regionalization Effects 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 30
- 150000004767 nitrides Chemical class 0.000 description 13
- 239000000758 substrate Substances 0.000 description 6
- 241000293849 Cordylanthus Species 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明の目的は、多結晶シリコン膜を選択的に
酸化する際、バード・ヘツド、バード・ビークの
少ない、マスク・パターンに忠実な選択酸化の方
法を提供することにある。DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to provide a method of selective oxidation that faithfully follows a mask pattern, with fewer bird heads and bird's beaks when selectively oxidizing a polycrystalline silicon film. be.
従来より、シリコン窒化膜を酸化マスクとして
シリコン基板表面の選択酸化をおこなうことは、
LOCOS構造もしくはISOPLANER構造において
広く用いられてきた。 Traditionally, selective oxidation of the silicon substrate surface using a silicon nitride film as an oxidation mask has been
It has been widely used in LOCOS or ISOPLANER structures.
しかし、近年、集積回路の密度が向上し、それ
にともなつて、パターンの微細化が進むにつれて
問題点が発生しつつある。以下に従来例のプロセ
スについて、図に従つて説明するとともに問題点
を列記する。第１図は、この製造工程を示すプロ
セス・フローである。図において、まず、シリコ
ン基板１に全面にシリコン窒化膜（Si3N4）２を
CVD法により形成する。次に、この上にフオ
ト・レジスト３を塗布し、選択酸化用フオト・マ
スクを用いて、レジスト・パターンを形成する。
次に、このレジストをマスクとして、シリコン窒
化膜２をエツチングし、レジスト・パターンを窒
化膜パターンに転写する。この状態を第１図ａに
示す。この場合、シリコン基板１とシリコン窒化
膜２の間に薄い（〜500Å）酸化膜を形成してお
く場合もある。この後レジスト３を除去し、酸化
雰囲気中で加熱すると、シリコン窒化膜中は酸素
が拡散せず、酸化防止膜として作用するので、窒
化膜が除去された領域にのみ酸化膜４が成長す
る。次に、窒化膜を加熱したりン酸中で（〜150
℃）窒化膜を除去することにより選択酸化工程は
終了する。 However, in recent years, as the density of integrated circuits has increased and patterns have become finer, problems have been occurring. Below, the conventional process will be explained with reference to the drawings, and problems will be listed. FIG. 1 is a process flow showing this manufacturing process. In the figure, first, a silicon nitride film (Si 3 N 4 ) 2 is deposited on the entire surface of a silicon substrate 1.
Formed by CVD method. Next, a photoresist 3 is applied thereon, and a resist pattern is formed using a photomask for selective oxidation.
Next, using this resist as a mask, the silicon nitride film 2 is etched, and the resist pattern is transferred to the nitride film pattern. This state is shown in FIG. 1a. In this case, a thin (~500 Å) oxide film may be formed between the silicon substrate 1 and the silicon nitride film 2. Thereafter, when resist 3 is removed and heated in an oxidizing atmosphere, oxygen does not diffuse into the silicon nitride film and acts as an oxidation prevention film, so oxide film 4 grows only in the region where the nitride film has been removed. Next, the nitride film is heated or in phosphoric acid (~150
℃) The selective oxidation process is completed by removing the nitride film.
以上のように、シリコン窒化膜をマスクとして
シリコン基板表面を選択的に酸化する絶縁分離方
法が従来よりおこなわれているが、この場合、酸
化膜とシリコン面の境界領域では、必ずしも、一
様に酸化膜が形成されている訳ではない。詳細に
見ると第１図ｃのような構造を示している。同図
ｃにおいて、窒化膜２は、端面において、２１の
ようにめくれあがり、その下部にもぐりこむよう
に酸化膜４１が成長している。通常これは、バー
ド・ビークと呼ばれているものである。また、こ
のバード・ビークの上部には、バード・ヘツドと
呼ばれる突起状の酸化膜４２が存在している。こ
れは酸素の拡散が等方的に起こること、シリコン
が酸化されると約２倍に体積が膨張することに起
因するもので、表面の一様性とパターン中のマス
クに対する忠実度をそこなつていて、選択酸化の
問題点となつている。 As described above, insulation isolation methods have been used in the past that selectively oxidize the silicon substrate surface using a silicon nitride film as a mask, but in this case, the boundary region between the oxide film and the silicon surface is not always uniformly It does not mean that an oxide film is formed. A closer look shows a structure as shown in Figure 1c. In FIG. 3C, the nitride film 2 is turned up at the end surface as shown in 21, and the oxide film 41 is grown to sneak under the nitride film 2. This is usually what is called a bird's beak. Further, above the bird's beak, there is a protruding oxide film 42 called a bird's head. This is due to the fact that oxygen diffusion occurs isotropically and the volume expands approximately twice when silicon is oxidized, which impairs the uniformity of the surface and the fidelity to the mask in the pattern. This is a problem with selective oxidation.
多結晶シリコン膜の選択酸化においても同様の
問題点が生じている。 Similar problems occur in selective oxidation of polycrystalline silicon films.
多結晶シリコン膜を選択酸化する必要性は、
MOS型電界効果トランジスタの多結晶シリコン
ゲート、もしくは多結晶シリコン配線パターンを
形成する工程で生じている。通常これらの、多結
晶シリコン・パターンの形成は、第２図ａに示す
ように、多結晶シリコン膜１３上にフオト・レジ
スト・パターン３１，３２を形成し、これをマス
クとして多結晶シリコン膜１３をエツチングして
おこなつている。これを多結晶シリコン膜の選択
酸化でおこなう場合は、第２図ｂに示すように多
結晶シリコン膜１３の上に窒化シリコン膜４を形
成し、この上にフオト・レジスト・パターン３
１，３２を出したあと、このレジストをマスクと
して窒化シリコン膜４をエツチングし、さらにこ
の窒化シリコン膜をマスクとして多結晶シリコン
膜の酸化をおこなつて形成している。 The need to selectively oxidize polycrystalline silicon films is
This occurs during the process of forming a polycrystalline silicon gate of a MOS field effect transistor or a polycrystalline silicon wiring pattern. Normally, these polycrystalline silicon patterns are formed by forming photoresist patterns 31 and 32 on the polycrystalline silicon film 13, and using these as a mask, as shown in FIG. 2a, the polycrystalline silicon film 13 is This is done by etching. When performing this by selective oxidation of a polycrystalline silicon film, a silicon nitride film 4 is formed on the polycrystalline silicon film 13 as shown in FIG. 2b, and a photoresist pattern 3 is formed on this.
1 and 32, the silicon nitride film 4 is etched using this resist as a mask, and the polycrystalline silicon film is further oxidized using this silicon nitride film as a mask.
この場合でも、第１図のシリコンの選択酸化の
場合と同様に、窒化膜の端部の酸化膜との界面に
おいて、バード・ビーク・、バード・ヘツドが発
生し、問題を生じている。 In this case as well, as in the case of selective oxidation of silicon shown in FIG. 1, bird beaks and bird heads occur at the interface with the oxide film at the edge of the nitride film, causing problems.
本発明は、従来における上述のような問題を解
消し、多結晶シリコン膜を窒化シリコン膜を酸化
マスクとして、選択酸化する際、バード・ビー
ク、バード・ヘツドの小さい、酸化膜を形成する
方法を提供するものである。これは、パターン・
サイズ・マスクの設計基準が３〜4μｍ以下の微
細パターンを有するLSI、超LSIでは、パターン
の忠実度に大きな効果をもたらし、高精度のLSI
プロセスにおいて、極めて要望の高い技術であ
る。 The present invention solves the above-mentioned conventional problems and provides a method for forming an oxide film with small bird's beak and bird's head when selectively oxidizing a polycrystalline silicon film using a silicon nitride film as an oxidation mask. This is what we provide. This is a pattern
In LSI and VLSI, which have fine patterns with a size mask design standard of 3 to 4 μm or less, it has a large effect on pattern fidelity, and is highly accurate.
This is a highly desired technology in the process.
本発明は、多結晶シリコン膜を選択酸化する
際、多結晶シリコン膜上に窒化シリコン膜を形成
し、フオト・エツチングを用いて前記窒化シリコ
ン膜の選択酸化用パターンを形成したのち、さら
にこの上に薄い多結晶シリコン膜を形成し、酸化
をおこなうものである。この構成によつて、窒化
膜パターンに忠実な選択酸化膜の形成を可能とす
るものである。 In the present invention, when selectively oxidizing a polycrystalline silicon film, a silicon nitride film is formed on the polycrystalline silicon film, and a pattern for selective oxidation of the silicon nitride film is formed using photo etching. In this method, a thin polycrystalline silicon film is formed and oxidized. This configuration makes it possible to form a selective oxide film faithful to the nitride film pattern.
以下に本発明の実施例について、図に従つて説
明する。第３図は、本発明による実施例のプロセ
スフローを示す。 Examples of the present invention will be described below with reference to the drawings. FIG. 3 shows a process flow of an embodiment according to the invention.
図に示すように、まず、シリコン基板１上にシ
リコンの選択酸化法によつてフイールド酸化膜２
１を〜8000Åの厚さに形成する。次にトランジス
タを形成すべき活性領域にゲート酸化膜２２を〜
1000Åの厚さに、酸化形成する。この状態を第３
図ａに示す。次にこの上から、多結晶シリコン膜
１３を〜4000Åの厚さに、CVD法により堆積し、
さらに、この上に窒化シリコン膜４を〜1200Åの
厚さに積層堆積させる。 As shown in the figure, first, a field oxide film 2 is formed on a silicon substrate 1 by a silicon selective oxidation method.
1 to a thickness of ~8000 Å. Next, a gate oxide film 22 is deposited on the active region where a transistor is to be formed.
Oxide is formed to a thickness of 1000 Å. This state is the third
Shown in Figure a. Next, a polycrystalline silicon film 13 is deposited on top of this to a thickness of ~4000 Å using the CVD method.
Further, a silicon nitride film 4 is deposited thereon to a thickness of about 1200 Å.
次に、フオト・レジストを全面塗布し、多結晶
シリコン・パターンのフオト・マスクを用いてフ
オト・レジストに露光・現像し、レジスト・パタ
ーンを形成する。第３図ｂにこの状態を示す。図
において５１はレジストパターンのゲート部分、
５２は配線部分を示している。本工程において、
多結晶シリコン膜３と窒化シリコン膜４の間に、
薄い（〜500Å）酸化膜を形成しておく場合があ
る。 Next, a photoresist is applied to the entire surface, and the photoresist is exposed and developed using a polycrystalline silicon pattern photomask to form a resist pattern. This state is shown in FIG. 3b. In the figure, 51 is the gate part of the resist pattern;
Reference numeral 52 indicates a wiring portion. In this process,
Between the polycrystalline silicon film 3 and the silicon nitride film 4,
A thin (~500 Å) oxide film may be formed in advance.
次に、レジストパターン５１，５２をマスクと
して窒化シリコン膜４をCF4プラズマによるドラ
イ・エツチングを用いてエツチングし、レジス
ト・パターンを窒化シリコン膜パターンに転写す
る。次にレジストを除去したのち、この上に第２
の多結晶シリコン膜６を全面に〜500Å堆積する。
この状態を第３図ｃに示す。なおこの場合、窒化
シリコン膜４をドライエツチングしたのち、さら
に多結晶シリコン１３を一部エツチングしておい
てもよい。これは、多結晶シリコンが酸化される
際、〜２倍に厚さが増加するが、酸化後、できる
だけ表面を平担にするため、あらかじめ、多結晶
シリコン膜を〜1/2の厚さにエツチングしておき、
２倍の厚さになつた時、酸化膜厚が多結晶シリコ
ン膜と略々同じになるよう調整するためである。 Next, the silicon nitride film 4 is etched using dry etching using CF 4 plasma using the resist patterns 51 and 52 as a mask, and the resist pattern is transferred to the silicon nitride film pattern. Next, after removing the resist, apply a second layer on top of this.
A polycrystalline silicon film 6 of ~500 Å is deposited over the entire surface.
This state is shown in FIG. 3c. In this case, after dry etching the silicon nitride film 4, a portion of the polycrystalline silicon 13 may be further etched. This is because when polycrystalline silicon is oxidized, the thickness increases by ~2 times, but in order to make the surface as flat as possible after oxidation, the polycrystalline silicon film is reduced to ~1/2 the thickness in advance. Etch it and
This is to adjust the thickness of the oxide film to be approximately the same as that of the polycrystalline silicon film when the thickness is doubled.
次に図ｃの状態で、全体を酸化雰囲気中で熱処
理し多結晶シリコンを全部酸化する。もちろんこ
の時、窒化シリコンにおおわれた領域は酸化され
ず、選択酸化がおこなわれる。次に、窒化シリコ
ン膜上の、多結晶シリコンが酸化膜となつた領域
をエツチングし、窒化膜を露出させる。この時同
時に、窒化膜がない領域の酸化膜も同じ厚さだけ
エツチングされ、その分だけ酸化膜の厚さが減少
する。次に、この窒化シリコン膜を熱リン酸（〜
160℃）中でエツチングすることにより選択酸化
が完成する。この状態を第３図ｄに示す。 Next, in the state shown in Figure c, the entire structure is heat treated in an oxidizing atmosphere to completely oxidize the polycrystalline silicon. Of course, at this time, the region covered with silicon nitride is not oxidized, but selective oxidation is performed. Next, the region on the silicon nitride film where the polycrystalline silicon has become an oxide film is etched to expose the nitride film. At this time, the oxide film in the area where the nitride film is not present is also etched to the same thickness, and the thickness of the oxide film is reduced by that amount. Next, this silicon nitride film was heated with hot phosphoric acid (~
Selective oxidation is completed by etching at 160°C. This state is shown in FIG. 3d.
以後、通常の工程を通すことにより、高精度の
MOS集積回路が形成される。 After that, high precision is achieved by passing through the normal process.
A MOS integrated circuit is formed.
本工程のように、通常の選択酸化の場合は、自
由空間にさらされている窒化膜が、酸化により端
部でめくれあがるように変形する場合と異なり、
窒化膜上に形成された多結晶シリコン膜の酸化膜
によつて、変形が防止され、かつ酸素の横方向へ
の拡散が防止されるために、酸化膜のバード・ヘ
ツド、バード・ビークが小さく、パターン精度の
良好な多結晶シリコン膜の選択酸化が実施できる
ようになつた。この結果ゲート長１〜2μｍの極
めて短チヤネルのMOS型トランジスタの形成が
可能となり、超LSIのプロセスに大きな貢献をし
ている。 In the case of normal selective oxidation like this process, unlike the case where the nitride film exposed to free space is deformed by oxidation so that it curls up at the end,
The oxide film of the polycrystalline silicon film formed on the nitride film prevents deformation and lateral diffusion of oxygen, so the bird head and bird beak of the oxide film are small. , selective oxidation of polycrystalline silicon films with good pattern accuracy has become possible. As a result, it has become possible to form extremely short channel MOS transistors with gate lengths of 1 to 2 μm, making a major contribution to the VLSI process.
以上のように本発明によると窒化膜パターンに
忠実な多結晶シリコンの選択酸化が可能となつ
た。 As described above, according to the present invention, it has become possible to selectively oxidize polycrystalline silicon faithful to the nitride film pattern.
第１図ａ，ｂ，ｃは従来の選択酸化法において
バード・ビーク、バード・ヘツドが形成されてい
る状態を示す断面図、第２図ａ，ｂは同じく従来
の選択酸化法における多結晶シリコンパターンの
形成過程を示す断面図、第３図ａ，ｂ，ｃ，ｄは
本発明の一実施例における多結晶シリコンの選択
酸化プロセスを示す断面図である。
１……シリコン基板、３……レジスト、４……
窒化シリコン膜、６，１３……多結晶シリコン
膜、２１……フイールド酸化膜、３１，３２……
レジストパターン。
Figures 1a, b, and c are cross-sectional views showing the formation of bird's beak and bird's head in the conventional selective oxidation method, and Figures 2a and b are cross-sectional views of polycrystalline silicon in the conventional selective oxidation method. FIGS. 3A, 3B, 3D, and 3D are sectional views showing the process of forming a pattern. 1...Silicon substrate, 3...Resist, 4...
Silicon nitride film, 6, 13... Polycrystalline silicon film, 21... Field oxide film, 31, 32...
resist pattern.
Claims (1)
のシリコン膜上にシリコン窒化膜を形成し、シリ
コン窒化膜による選択酸化用パターンを形成する
工程、第２のシリコン膜を上記第１のシリコン膜
および上記シリコン窒化膜上の全面に形成する工
程、上記第２のシリコン膜および、選択酸化用パ
ターン形成においてシリコン窒化膜の除去された
領域の上記第１のシリコン膜を酸化する工程、上
記第２のシリコン膜が酸化されて形成された酸化
膜を除去する工程、上記シリコン窒化膜を除去す
る工程の各工程を順次行なつて前記第１のシリコ
ン膜を選択的に酸化することを特徴とする選択酸
化方法。 ２ 特許請求の範囲第１項の記載において、第１
のシリコン膜がシリコン多結晶膜であることを特
徴とする選択酸化方法。 ３ 特許請求の範囲第１項の記載において、シリ
コン窒化膜と第１のシリコン膜の間に、薄いシリ
コン酸化膜を形成することを特徴とする選択酸化
方法。[Claims] 1. A step of forming a first silicon film;
forming a silicon nitride film on the silicon film and forming a selective oxidation pattern using the silicon nitride film; forming a second silicon film on the entire surface of the first silicon film and the silicon nitride film; oxidizing the second silicon film and the first silicon film in the area where the silicon nitride film was removed in selective oxidation pattern formation; A selective oxidation method characterized in that the first silicon film is selectively oxidized by sequentially performing the steps of removing the silicon nitride film and removing the silicon nitride film. 2 In the statement of claim 1, the first
A selective oxidation method characterized in that the silicon film is a silicon polycrystalline film. 3. The selective oxidation method according to claim 1, characterized in that a thin silicon oxide film is formed between the silicon nitride film and the first silicon film.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55179443A JPS57102046A (en) | 1980-12-17 | 1980-12-17 | Selective oxidation |
| US06/466,142 US4465705A (en) | 1980-05-19 | 1983-02-14 | Method of making semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55179443A JPS57102046A (en) | 1980-12-17 | 1980-12-17 | Selective oxidation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57102046A JPS57102046A (en) | 1982-06-24 |
| JPS6338863B2 true JPS6338863B2 (en) | 1988-08-02 |
Family
ID=16065946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55179443A Granted JPS57102046A (en) | 1980-05-19 | 1980-12-17 | Selective oxidation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57102046A (en) |
-
1980
- 1980-12-17 JP JP55179443A patent/JPS57102046A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57102046A (en) | 1982-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6228578B2 (en) | ||
| JPS59139643A (en) | Semiconductor device and manufacture thereof | |
| JPS59135743A (en) | Semiconductor device and manufacture thereof | |
| JPS59165434A (en) | Manufacture of semiconductor device | |
| JPS6338863B2 (en) | ||
| JPS6242382B2 (en) | ||
| EP0120614A1 (en) | Method of manufacturing a semiconductor device having isolation regions | |
| JPH06326091A (en) | Formation method for field oxide film in semiconductor element | |
| JPS5844735A (en) | Manufacture of semiconductor device | |
| JPH0413854B2 (en) | ||
| JPH06163528A (en) | Fabrication of semiconductor device | |
| JPS5992547A (en) | Isolation process | |
| JPH05206263A (en) | Manufacture of semiconductor device | |
| JP3058943B2 (en) | Method for manufacturing semiconductor device | |
| JPH0338733B2 (en) | ||
| JPH05218193A (en) | Manufacture of semiconductor device | |
| JP3042804B2 (en) | Element isolation method and semiconductor device | |
| JPS6227746B2 (en) | ||
| JPS6142425B2 (en) | ||
| JPH02142117A (en) | Manufacture of semiconductor integrated circuit | |
| JPS6141136B2 (en) | ||
| KR100418299B1 (en) | Method for forming field oxide layer of semiconductor device | |
| JPH0210729A (en) | Formation of field insulating film | |
| JPS60136329A (en) | Manufacture of semiconductor device | |
| JPH0521423A (en) | Manufacture of semiconductor device |