JPS6336545B2 - - Google Patents

Info

Publication number
JPS6336545B2
JPS6336545B2 JP58049254A JP4925483A JPS6336545B2 JP S6336545 B2 JPS6336545 B2 JP S6336545B2 JP 58049254 A JP58049254 A JP 58049254A JP 4925483 A JP4925483 A JP 4925483A JP S6336545 B2 JPS6336545 B2 JP S6336545B2
Authority
JP
Japan
Prior art keywords
lock
lock request
request
processor
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58049254A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59173866A (ja
Inventor
Susumu Shibazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58049254A priority Critical patent/JPS59173866A/ja
Publication of JPS59173866A publication Critical patent/JPS59173866A/ja
Publication of JPS6336545B2 publication Critical patent/JPS6336545B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
JP58049254A 1983-03-24 1983-03-24 ロツク制御方式 Granted JPS59173866A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58049254A JPS59173866A (ja) 1983-03-24 1983-03-24 ロツク制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58049254A JPS59173866A (ja) 1983-03-24 1983-03-24 ロツク制御方式

Publications (2)

Publication Number Publication Date
JPS59173866A JPS59173866A (ja) 1984-10-02
JPS6336545B2 true JPS6336545B2 (fr) 1988-07-20

Family

ID=12825694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58049254A Granted JPS59173866A (ja) 1983-03-24 1983-03-24 ロツク制御方式

Country Status (1)

Country Link
JP (1) JPS59173866A (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS626366A (ja) * 1985-07-03 1987-01-13 Hitachi Ltd 記憶制御方式
JPS6367670A (ja) * 1986-09-09 1988-03-26 Fujitsu Ltd システム間共用資源占有情報管理処理方式
US5341510A (en) * 1987-05-01 1994-08-23 Digital Equipment Corporation Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor
DE3884606T2 (de) * 1987-05-01 1994-03-17 Digital Equipment Corp Steuerungsknotenverfahren und -anordnung zur sicherung eines angepassten zugriffs zu betriebsmitteln in einem multiprozessordatenverarbeitungssystem.
US4937733A (en) * 1987-05-01 1990-06-26 Digital Equipment Corporation Method and apparatus for assuring adequate access to system resources by processors in a multiprocessor computer system

Also Published As

Publication number Publication date
JPS59173866A (ja) 1984-10-02

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