JPS633463B2 - - Google Patents
Info
- Publication number
- JPS633463B2 JPS633463B2 JP53107043A JP10704378A JPS633463B2 JP S633463 B2 JPS633463 B2 JP S633463B2 JP 53107043 A JP53107043 A JP 53107043A JP 10704378 A JP10704378 A JP 10704378A JP S633463 B2 JPS633463 B2 JP S633463B2
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead
- lead frame
- thin metal
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 11
- 230000000694 effects Effects 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Description
【発明の詳細な説明】
本発明は改良された半導体装置用リードフレー
ムに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved lead frame for a semiconductor device.
樹脂封止型半導体装置は、その量産性及び低価
格ゆえに広く採用されている。そして本装置はリ
ードフレームを用いて製造するのが一般的であ
る。このリードフレームは、例えば第１図の平面
図に示すように、コバール等の金属薄板を写真蝕
刻法あるいはプレス加工により、外枠１ａ，１ｂ
間に半導体素子２を固着するための素子載置部
３、リード４ａ，４ｂ………、そのリードを固定
している内枠５が一体的に形成されている。リー
ド４ａ，４ｂ………、はその本数が14本、16本、
20本等半導体装置の違いにより各種のものが使用
されている。 Resin-sealed semiconductor devices are widely used because of their mass productivity and low cost. This device is generally manufactured using a lead frame. For example, as shown in the plan view of FIG. 1, this lead frame is made by photo-etching or press working a thin metal plate such as Kovar to form outer frames 1a and 1b.
An element mounting portion 3 for fixing the semiconductor element 2 therebetween, leads 4a, 4b, and an inner frame 5 to which the leads are fixed are integrally formed. The number of leads 4a, 4b, etc. is 14, 16,
20 different types are used depending on the semiconductor device.
ここでは14本のリードを有するリードフレーム
について説明する。このリードフレームに対して
13個の電極を有する半導体素子２を組立てる場
合、例えばリード４ｂには金属細線接続をする必
要がないとすると、他の13本のリード４ａ，４
ｃ，４ｄ………に金属細線６を介して半導体素子
の電極とリードとが接続される。 Here, a lead frame with 14 leads will be explained. for this lead frame
When assembling the semiconductor element 2 having 13 electrodes, for example, if it is not necessary to connect the lead 4b with a thin metal wire, the other 13 leads 4a, 4
The electrodes and leads of the semiconductor element are connected to terminals c, 4d, . . . via thin metal wires 6.
このようなリードフレームの場合、接続を行わ
ないリード４ｂも他のリード４ａ，４ｃ，４ｄ…
……とその先端位置が同様の位置に形成されてい
るため、金属細線接続部の先端幅ｌが狭くなり、
リード４ａ，４ｃ………への金属細線接続を正確
に行うことは難しくなつてくる。 In the case of such a lead frame, the lead 4b that is not connected also connects to the other leads 4a, 4c, 4d...
...and their tips are formed in the same position, so the tip width l of the thin metal wire connection becomes narrower.
It is becoming difficult to accurately connect the thin metal wires to the leads 4a, 4c, . . . .
特に40本、42本等の本数の多いリードを有する
リードフレームの場合は特に問題になつてくる。 In particular, this becomes a problem in the case of a lead frame having a large number of leads, such as 40 or 42 leads.
本発明は以上の点を改善した樹脂封止型半導体
装置用リードフレームを提供するものである。 The present invention provides a lead frame for a resin-sealed semiconductor device that improves the above points.
即ち、金属薄板を写真蝕刻又はプレス加工によ
り、金属細線を接続しないリードは、その先端位
置を他のリードの先端位置より後方に下げ、生じ
た間隙を他のリードの内部先端幅を広げて補填せ
しめたリードフレームを提供する。 That is, by photo-etching or press working a thin metal plate, the tip position of the lead that does not connect the thin metal wire is lowered to the rear of the tip position of the other leads, and the gap created is compensated for by widening the internal tip width of the other leads. We provide finished lead frames.
このようにして製作されたリードフレームを使
用すれば、素子載置部に素子を固着し、次に素子
と外部リードとを金属細線を介して接続する場
合、リードの金属細線接続部の先端幅ｌが広いの
で接続位置ズレに対して有利となり、歩留り良く
金属細線の接続を行うことができる。 If you use the lead frame manufactured in this way, when you fix the element on the element mounting part and then connect the element and external leads via the thin metal wire, the width of the tip of the thin metal wire connection part of the lead Since l is wide, it is advantageous against misalignment of the connection position, and thin metal wires can be connected with high yield.
以下、実施例について説明する。第２図は本発
明によるリードフレームの平面図を示す。250μ
ｍ厚のコバール薄板を、写真蝕刻法により外枠１
ａ，１ｂ間に半導体素子を固着するための素子載
置部３、外部リード４ａ，４′，４ｃ，４ｄ，…
……、外部リードを固定している内枠５がそれぞ
れ設けられ、金属細線を接続しないリード４′は
その先端位置を他のリード４ａ，４ｃ，………の
先端より後方に下げた位置に形成しておく。この
ことにより従来第１図における素子載置部３の上
辺の右部の２本（４ａ，４ｂ）と右辺の３本（４
ｃ，４ｄ、その隣の１本）との合計５本で占めて
いた位置が、本実施例では第２図のように４本
（４ａ，４ｃ，４ｄ、その隣の１本）になるので
各リード先端の幅を約20％程度広くすることがで
きる。 Examples will be described below. FIG. 2 shows a top view of a lead frame according to the invention. 250μ
The outer frame 1 is made of a thin Kovar plate with a thickness of m by photolithography.
An element mounting part 3 for fixing a semiconductor element between a and 1b, external leads 4a, 4', 4c, 4d, . . .
. . ., an inner frame 5 for fixing the external leads is provided, and the tip of the lead 4' to which the thin metal wire is not connected is lowered to the rear than the tips of the other leads 4a, 4c, . Form it. As a result, the two (4a, 4b) on the right side and the three (4) on the right side of the upper side of the element mounting portion 3 in FIG.
The position occupied by a total of 5 wires (4a, 4d, 1 wire next to them) is now reduced to 4 wires (4a, 4c, 4d, 1 wire next to them) as shown in FIG. 2 in this embodiment. The width of each lead tip can be increased by about 20%.
このようにして製作されたリードフレームは、
金属細線接続部のリード先端幅ｌが従来と比較し
て広くなり、歩留り良く金属細線接続を行うこと
ができる。このようにリード内部の集中した先端
部は非常に密集しているので、その内の１本が減
るだけでもかなり効果が出る。 The lead frame manufactured in this way is
The width l of the lead tip of the thin metal wire connecting portion is wider than that of the conventional method, and the thin metal wire can be connected with high yield. In this way, the concentrated tips inside the leads are very densely packed, so even if only one of them is removed, a considerable effect can be obtained.
本発明では、説明を簡単にするため14本のリー
ドを有するリードフレームについて述べたが、多
数のリード例えば40本あるいは42本のリードを有
するようなリードフレームに於いては効果がさら
に大きくなる。 In the present invention, a lead frame having 14 leads has been described to simplify the explanation, but the effect will be even greater in a lead frame having a large number of leads, for example, 40 or 42 leads.
第１図は従来のリードフレームの平面図を、第
２図は本発明によるリードフレームの平面図をそ
れぞれ示す。
１ａ，１ｂ……外枠、２……半導体素子、３…
…素子載置部、４ａ，４ｃ，４ｄ……リード、４
ｂ，４′……細線接続しないリード、５……内枠、
６……金属細線。
FIG. 1 shows a plan view of a conventional lead frame, and FIG. 2 shows a plan view of a lead frame according to the present invention. 1a, 1b...Outer frame, 2...Semiconductor element, 3...
...Element mounting part, 4a, 4c, 4d...Lead, 4
b, 4'... Leads that do not connect thin wires, 5... Inner frame,
6...Thin metal wire.
Claims (1)
ドと、素子と接続しないリードとを含む半導体装
置用リードフレームにおいて、前記素子と接続し
ないリードの先端部を、前記素子と接続するリー
ドの先端部よりも前記素子載置部から長距離離隔
せしめたことを特徴とする半導体装置用リードフ
レーム。1. In a lead frame for a semiconductor device that includes a lead that connects to an element with an element mounting part and a thin metal wire, and a lead that does not connect to the element, the tip of the lead that does not connect to the element is replaced with the tip of the lead that connects to the element. A lead frame for a semiconductor device, characterized in that the lead frame is separated from the element mounting part by a longer distance than the element mounting part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10704378A JPS5534453A (en) | 1978-08-31 | 1978-08-31 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10704378A JPS5534453A (en) | 1978-08-31 | 1978-08-31 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5534453A JPS5534453A (en) | 1980-03-11 |
| JPS633463B2 true JPS633463B2 (en) | 1988-01-23 |
Family
ID=14449064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10704378A Granted JPS5534453A (en) | 1978-08-31 | 1978-08-31 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5534453A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6234454Y2 (en) * | 1980-09-30 | 1987-09-02 | ||
| JPS60123118A (en) * | 1983-12-06 | 1985-07-01 | Toyo Commun Equip Co Ltd | Package of piezoelectric oscillator or the like |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS522168A (en) * | 1975-06-24 | 1977-01-08 | Hitachi Ltd | Composite molding machine |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132264U (en) * | 1974-08-30 | 1976-03-09 | ||
| JPS53100875U (en) * | 1977-01-19 | 1978-08-15 |
-
1978
- 1978-08-31 JP JP10704378A patent/JPS5534453A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS522168A (en) * | 1975-06-24 | 1977-01-08 | Hitachi Ltd | Composite molding machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5534453A (en) | 1980-03-11 |
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