JPS6333288B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to chip-shaped porcelain capacitors and capacitor assemblies.

Chip-shaped porcelain capacitors are easy to make small and large in capacity, can be directly bonded to a flat conductive pattern and meet the demands of high-density packaging, and exhibit excellent frequency characteristics up to high frequencies.
Furthermore, it has excellent features such as having a unified external shape and being able to be automatically mounted and assembled when mounted on a printed circuit board, etc. Recently, ultra-thin radios,
With the increasing sophistication and high-density packaging of electronic and electrical equipment such as tape recorders, calculators, and electronic tuners,
Its usage continues to increase.

FIG. 1 shows a conventional example of a chip-shaped ceramic capacitor, in which electrodes 2 and 3 are formed on both sides of a dielectric ceramic 1 with a thickness of about 50 to 100 μm, the main component of which is barium titanate or titanium oxide. Electrodes 2, 3
The opposite ends of the dielectric ceramic 1 are electrically connected to end electrodes 4 and 5 formed at both ends of the dielectric ceramic 1, respectively. 6, in order to ensure the insulation properties of the electrodes 2 and 3 and chemical resistance against soldering flux,
A protective layer formed on the surfaces of the electrodes 2 and 3, and made of glass or synthetic resin.

In order to increase the acquired capacitance in the conventional chip-shaped ceramic capacitor described above, in addition to using a high dielectric constant ceramic material as the dielectric ceramic 1 and increasing the overlapping area of the electrodes 2 and 3, It is effective to make the thickness t between 2 and 3 as thin as possible. However, with the single-plate structure as described above, the smaller the thickness t between the electrodes 2 and 3, the lower the mechanical strength of the dielectric porcelain 1, and the more likely it is that the dielectric porcelain 1 will be damaged, cracked, etc. This tends to occur, and the thermal shock resistance during soldering etc. decreases, so there is a limit to the increase in the acquired capacitance by reducing the thickness between the electrodes 2-3. Also, since the dielectric porcelain 1 will warp due to firing, it is necessary to give the dielectric porcelain 1 a certain amount of thickness in order to absorb this warp. There is a limit.

By eliminating these conventional drawbacks and increasing capacity by reducing the electrode spacing without reducing mechanical strength, we have created a highly reliable capacitor with improved thermal shock resistance, as shown in Figure 2. Chip-shaped porcelain capacitors have been proposed.

This chip-shaped ceramic capacitor is provided with an electrode 2 on one surface of a dielectric ceramic 1 formed in a flat plate shape, and an electrode 2 is provided inside the dielectric ceramic 1 by several microns to several tens of microns from the surface on which the electrode 2 is formed. The internal electrode 7 is buried through a dielectric ceramic layer 1A having a layer thickness of , and the internal electrode 7 is lined and reinforced with a dielectric ceramic layer 1B having a thickness of, for example, about 100μ to 1000μ. .

As mentioned above, in the chip-shaped ceramic capacitor shown in FIG. 2, the back of the internal electrode 7 is lined and reinforced with the dielectric ceramic layer 1B.
While increasing the capacity by thinning the dielectric ceramic layer 1,
The decrease in mechanical strength due to the thinning of A is compensated for by the dielectric ceramic layer 1B, and it is possible to increase the capacity without reducing the overall thickness or mechanical strength. Furthermore, since the internal electrode 7 is sealed with the dielectric ceramic layers 1A and 1B, the heat shock resistance during soldering of the end electrodes 4 and 5 is improved, and the internal electrode 7
The phenomenon of solder eating is prevented, and interfacial peeling can be almost completely prevented.

However, since the electrode 2 paired with the internal electrode 7 was provided on the surface of the dielectric ceramic 1 and the protective layer 6 was coated on the surface, there were the following drawbacks.

(1) Solder eating of the electrode 2, cracks caused by heat shock during soldering, and interfacial peeling of the electrode 2 could not be prevented, resulting in reliability problems.

(2) The dielectric ceramic layers 1A, 1B and the electrodes 2, 7 can be laminated in an integrated process using a thick film manufacturing technique such as a sheet lamination method or a screen printing lamination method.
Since the protective layer 6 needs to be made of glass or synthetic resin, which is different from dielectric porcelain in terms of material,
It must be formed in a separate process, which complicates the manufacturing process and increases manufacturing costs.

(3) Due to the difference in materials between the protective layer 6 and the dielectric ceramic 1, peeling occurs at the interface between the two, so the insulation, chemical resistance, etc. of the electrode 2 are likely to deteriorate due to moisture intrusion, reducing reliability. There is a problem.

Furthermore, this kind of chip-shaped porcelain capacitor is
Its flat area is very small, for example, about 3 x 5 m/m, and its thickness is about 1 mm, making it difficult to handle.Furthermore, there is a trend toward further miniaturization due to the demand for high-density packaging, and dielectric materials Porcelain layer 1
Due to unique circumstances such as the need to have a laminated structure of A and 1B, it is extremely difficult to manufacture a single ceramic capacitor from the beginning to the end of the manufacturing process. In addition, when multiple capacitors are required such as a lumped delay element, or when multiple capacitors are mounted on a printed circuit board, it is possible to combine the required number of chip-shaped ceramic capacitors that are individually manufactured. This requires a large number of assembly steps, increases costs, and is disadvantageous in terms of miniaturization and high packaging density.
Furthermore, when measuring the characteristics of the obtained chip-shaped porcelain capacitors and selecting only those that fall within standard values, it is necessary to measure and select the characteristics one by one, which is very cumbersome.

The present invention solves the above-mentioned technical problems, and provides a highly reliable and inexpensive chip-shaped porcelain capacitor that is easy to manufacture, does not cause the phenomenon of solder eating of the electrodes, the occurrence of cracks, or the phenomenon of interfacial peeling. The purpose is to provide.

Another object of the present invention is to provide a capacitor assembly that is convenient for handling, storage, etc., and can be used as a composite type of ceramic capacitor as well as being able to easily separate individual chip-shaped ceramic capacitors. .

To achieve the above object, the present invention provides a chip-shaped porcelain capacitor having end electrodes electrically connected to electrodes defining a substantial capacitance at opposite ends of a dielectric ceramic. Electrodes determining the substantial capacitance are embedded in layers inside the body porcelain, and one of the two outermost internal electrodes has a thickness that is greater than the layer thickness of the dielectric ceramic layer between the internal electrodes. is covered with a thick dielectric ceramic layer, and the other of the two internal electrodes is covered with a dielectric ceramic layer that is sufficiently thinner than the dielectric ceramic layer that covers one of the internal electrodes. Features.

Further, in the capacitor assembly according to the present invention, grooves are provided at intervals along the length of the dielectric ceramic substrate, and capacitor elements are provided in each region divided by the grooves. Each of the capacitor elements has electrodes that define the substantial capacitance buried inside the dielectric ceramic substrate in a layered manner, and one of the two inner electrodes located at the outermost side of the inner electrodes. is covered with a dielectric ceramic layer that is thicker than the dielectric ceramic layer between the internal electrodes, and the other of the two internal electrodes is sufficiently thinner than the dielectric ceramic layer that covers one of the internal electrodes. It is characterized in that it is covered with a thick dielectric ceramic layer, and end electrodes that are electrically connected to the internal electrodes are provided at both ends in the width direction.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The content of the present invention will be specifically described below with reference to the accompanying drawings, which are examples.

FIG. 3A is a plan view of a chip-shaped porcelain capacitor according to the present invention, and FIG. 3B is a front sectional view taken along line B ₁ -B ₁ in FIG. 3A. In the figures, the same reference numerals as in FIG. 2 indicate functionally identical components. As shown in the figure, in the present invention, electrodes 7 and 8 that define a substantial capacity are buried inside the dielectric ceramic 1 in a layered manner with the dielectric ceramic layer 1A interposed therebetween, and these two internal electrodes 7, One of 8,
That is, the internal electrode 7 is covered with the dielectric ceramic layer 1B which is thicker than the dielectric ceramic layer 1A between the internal electrodes 7-8, and the internal electrode 8 is covered with a dielectric ceramic layer 1B which is thicker than the dielectric ceramic layer 1B which covers the internal electrode 7. Dielectric ceramic layer 1 with a thin layer thickness
It has a structure covered by C. Internal electrode 8
As shown in the figure, the layer thickness of the dielectric ceramic layer 1C covering the internal electrodes 7-8 is set to be approximately equal to that of the dielectric ceramic layer 1A between the internal electrodes 7-8. With such a structure, not only the internal electrodes 7 but also the internal electrodes 8 are sealed inside the dielectric ceramic 1, resulting in a completely monolithic structure, which prevents the phenomenon of solder eating of the internal electrodes 7 and 8 and thermal damage. Occurrence of cracks due to shock, interfacial peeling phenomenon,
Deterioration due to oxidation is completely prevented, and reliability is significantly improved. Moreover, since the dielectric ceramic layer 1C on the upper surface of the internal electrode 8 serves as a protective layer, there is no possibility of interfacial peeling of the protective layer as in the conventional case, and reliability is improved. Furthermore, since the dielectric ceramic layer 1C can be formed in the same process as the lamination process of the other dielectric ceramic layers 1A and 1B, the manufacturing process is simplified.
Manufacturing costs become cheaper.

Moreover, the internal electrode 7 has a dielectric ceramic layer 1B thicker than the dielectric ceramic layer 1A between the internal electrodes 7-8.
Since the internal electrode 8 is covered with a dielectric ceramic layer 1C that is sufficiently thinner than the dielectric ceramic layer 1B that covers the internal electrode 7, during firing, Thermal stress strain caused by the dielectric ceramic layer 1C is significantly smaller than that of the internal electrodes 7 and 8 and the dielectric ceramic layers 1A and 1B below it. Therefore, delamination of the dielectric ceramic layer 1C due to thermal stress distortion is prevented, and a highly reliable chip-shaped ceramic capacitor can be obtained.

Further, in this embodiment, arcuate or diagonal missing portions 9 to 12 are provided at the corners of both ends of the dielectric ceramic 1 where the end electrodes 4 and 5 are provided. Providing such missing portions 9 to 12 makes it very easy to attach to the magazine and circuit board of the automatic placement machine.

Note that the internal electrodes 7 and 8 are made of platinum, palladium,
It is composed of an electrode material whose main component is a metal with a high melting point such as silver or an alloy thereof.

Next, FIG. 4A is a plan view of a capacitor assembly according to the present invention, FIGS. 4B and C are line B ₂ -B ₂ of FIG. 4A,
It is each sectional view on the _B3 - _B3 line. In the figure, 13 is a dielectric ceramic substrate. The dielectric ceramic substrate 13 is made of a high dielectric constant ceramic material such as barium titanate or titanium oxide.
At the same position on one or both sides, at a predetermined interval d ₁
A plurality of concave grooves _S1 are provided at the same time. Concave groove S ₁
These are dividing positions for dividing the dielectric ceramic substrate 13, and can be provided in a continuous line shape, a perforation shape, or a partially through hole shape that reaches from the front surface to the back surface of the substrate 13.

In each area divided by the groove _S1 ,
Mutually independent chip-shaped porcelain capacitor elements are each formed. Each of the chip-shaped ceramic capacitors has substantially the same structure as shown in FIGS. 14, 15, for example, behind the internal electrode 14, a dielectric ceramic layer 13 having a thickness thicker than the dielectric ceramic layer 13A between the internal electrodes 14-15.
It has a structure with B. The upper surface of the internal electrode 15 is sealed with a dielectric ceramic layer 13C serving as a protective layer. Further, arcuate or angular cutout portions 16 and 17 are provided at both ends of the groove _S1 , and the cutout portions 16 and 17 are provided at both ends of the groove S1.
At both ends of the dielectric ceramic substrate 13 divided by 17, end electrodes 18 and 19 are provided which are electrically connected to the internal electrodes 14 and 15, respectively.

Since the capacitor assembly according to the present invention has the above-described structure, it can be used in cases where a plurality of capacitors are required, such as a lumped delay element, or when it is necessary to mount a plurality of capacitors on a circuit board. The device can be used as is, and is extremely effective in reducing assembly man-hours, reducing costs, downsizing, and achieving high-density packaging. Moreover, as shown in FIG. 5, a single chip-shaped porcelain capacitor can be easily taken out by indexing along the groove _S1 . In addition, even though the chip-shaped ceramic capacitors are integrated via the dielectric ceramic substrate 13, they are electrically independent from each other, so it is possible to measure the characteristics and sort them while they are in an aggregate state. This greatly facilitates measurement and selection work. Furthermore, since the capacitor assembly is many times larger than a single capacitor, there is no risk of loss, it is convenient to handle and store, and it is easy to manufacture.

As described above, the present invention provides a chip-shaped porcelain capacitor having end electrodes electrically connected to electrodes defining substantial capacitance at opposite ends of a dielectric porcelain. Electrodes determining the substantial capacitance are buried inside the ceramic in a layered manner, and one of the two outermost internal electrodes has a thickness that is greater than the layer thickness of the dielectric ceramic layer between the internal electrodes. covered by a thick dielectric porcelain layer;
Since the other of the two internal electrodes is covered with a dielectric ceramic layer that is sufficiently thinner than the dielectric ceramic layer that covers one of the internal electrodes, the following effects can be obtained. be.

(1) It has a completely monolithic structure in which all of the electrodes that determine the actual capacitance are sealed inside the dielectric ceramic, which prevents solder erosion of the electrodes, cracks due to thermal shock, interfacial peeling phenomena, and deterioration due to oxidation. is completely prevented. Therefore, according to the present invention, it is possible to provide a highly reliable chip-shaped ceramic capacitor with stable characteristics.

(2) Since they can be manufactured by laminating the same dielectric ceramic materials, the manufacturing process is simplified and the manufacturing cost is reduced.

(3) One of the two outermost internal electrodes is covered with a dielectric ceramic layer that is thicker than the dielectric ceramic layer between the internal electrodes, which reduces the overall thickness and mechanical strength. It is possible to provide a chip-shaped porcelain capacitor with a large capacity without any problems.

(4) One of the two outermost internal electrodes is covered with a dielectric ceramic layer that is thicker than the dielectric ceramic layer between the internal electrodes, and the other of the two internal electrodes is covered with one of the internal electrodes. Since the dielectric ceramic layer is sufficiently thinner than the dielectric ceramic layer covering the other internal electrode, the thermal stress strain caused by the dielectric ceramic layer covering the other internal electrode will affect the internal electrode and dielectric layer below. It is significantly smaller than the body porcelain layer. Therefore, delamination of the dielectric ceramic layer due to thermal stress distortion can be prevented, and a highly reliable chip-shaped ceramic capacitor can be provided.

Further, in the capacitor assembly according to the present invention, grooves are provided at intervals along the length of the dielectric ceramic substrate, and capacitor elements are provided in each area divided by the grooves. Each of the capacitor elements has electrodes defining the substantial capacitance embedded in the dielectric ceramic substrate in a layered manner, and one of the two inner electrodes located at the outermost side of the inner electrodes. is covered with a dielectric ceramic layer that is thicker than the dielectric ceramic layer between the internal electrodes, and the other of the two internal electrodes is sufficiently thinner than the dielectric ceramic layer that covers one of the internal electrodes. Since it is characterized in that it is covered with a thick dielectric ceramic layer and provided with end electrodes that are electrically connected to the internal electrodes at both ends in the width direction, the following effects can be obtained.

(1) It is equipped with a plurality of highly reliable ceramic capacitors that have substantially the same structure and effect as the above-mentioned chip-shaped ceramic capacitor, and can be used as a component of a device that requires multiple capacitors such as a lumped delay element. A truly suitable capacitor assembly can be provided.

(2) By dividing along the grooves, any number of composite capacitors or chip-shaped porcelain capacitors as the smallest unit can be obtained very easily.

(3) Since a capacitor assembly is many times larger than a single capacitor, there is no risk of losing it, and it is extremely convenient to handle and store.

(4) Even though each capacitor element is integrated with a dielectric ceramic substrate, it is electrically independent from each other, and its characteristics can be measured and sorted in the aggregate state. This greatly facilitates the selection of good products.

Although each of the above embodiments has been described as having a pair of internal electrodes, the present invention is similarly applicable to a stacked type with more layers.

[Brief explanation of drawings]

1 is a sectional view of a conventional chip-shaped ceramic capacitor, FIG. 2 is a sectional view of a previously proposed chip-shaped porcelain capacitor, and FIG. 3A is a plan view of a chip-shaped porcelain capacitor according to the present invention. Figure B is the same as Figure 3A.
A sectional view taken along line B ₁ - B ₁ , FIG. 4A is a plan view of a capacitor assembly according to the present invention, and FIGS. 4B and C
4A are cross-sectional views taken along lines B ₂ -B ₂ and B ₃ -B ₃ in FIG. 4A, and FIG. 5 is a diagram illustrating a method for determining chip-shaped ceramic capacitors from a capacitor assembly according to the present invention. 1, 13...Dielectric ceramic layer, 1A, 13A...Dielectric ceramic layer, 1B, 13B...Dielectric ceramic layer, 1
C, 13C...dielectric ceramic layer, 4, 5, 18, 1
9... End electrode, 7, 8, 14, 15... Internal electrode, 9, 10, 11, 12... Missing part, S ₁ ... Concave groove.

Claims (1)

[Scope of Claims] 1. A chip-shaped porcelain capacitor having end electrodes electrically connected to electrodes defining a substantial capacity at opposite ends of a dielectric porcelain, wherein the inside of the dielectric porcelain is electrodes that determine the substantial capacity are buried in layers, one of the two outermost internal electrodes being made of a dielectric material having a thickness greater than the layer thickness of the dielectric ceramic layer between the internal electrodes. The chip is covered with a ceramic layer, and the other of the two internal electrodes is covered with a dielectric ceramic layer that is sufficiently thinner than the dielectric ceramic layer that covers one of the internal electrodes. shaped porcelain capacitor. 2. The chip-shaped porcelain according to claim 1, wherein the other of the two internal electrodes is covered with a dielectric porcelain layer having approximately the same thickness as the dielectric porcelain layer between the internal electrodes. capacitor. 3. The chip-shaped porcelain capacitor according to claim 1 or 2, wherein the dielectric ceramic has a cutout at the corner of both ends. 4 Recessed grooves are provided at intervals along the length of the dielectric ceramic substrate, and capacitor elements are provided in each region divided by the recessed grooves, and each of the capacitor elements is , electrodes defining the substantial capacitance are embedded in layers inside the dielectric ceramic substrate, and one of the two outermost internal electrodes is a dielectric ceramic layer between the internal electrodes. The other of the two internal electrodes is covered with a dielectric ceramic layer that is sufficiently thinner than the dielectric ceramic layer that covers one of the internal electrodes. What is claimed is: 1. A capacitor assembly comprising: a capacitor assembly covered with a capacitor; and end electrodes electrically connected to the internal electrodes provided at both ends in the width direction. 5. The capacitor assembly according to claim 4, wherein the end electrodes of the adjacent capacitor elements are electrically independent from each other. 6. A patent claim characterized in that each end electrode of the adjacent capacitor element is made electrically independent from each other by a cutout provided on both ends of the groove of the dielectric ceramic substrate. The capacitor assembly according to item 5.