JP2587851Y2 - Multilayer capacitors - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor having a structure in which a plurality of internal electrodes are arranged so as to overlap with each other via a dielectric layer. In particular, the present invention relates to a multilayer capacitor in which external electrodes are formed so as to enhance bonding reliability. To a multilayer capacitor.

[0002]

2. Description of the Related Art When a capacitor is incorporated together with an IC in a hybrid IC or the like, an electrode of the capacitor is often electrically connected to a terminal of the IC or a terminal of another component by a bonding wire. As the capacitors used for the above applications, the multilayer capacitor shown in FIG. 2 and the single-plate type capacitor shown in FIG. 3 are used.
The multilayer capacitor 1 of FIG. 2 has a structure in which internal electrodes 3 to 6 are formed in a dielectric chip 2 made of dielectric ceramics, and first and second external electrodes 7 and 8 are formed on the outer surface. . When the multilayer capacitor 1 is used for the above purpose, bonding wires 9a and 9b are bonded to the first and second external electrodes 7 and 8, respectively.

On the other hand, a single-plate type capacitor 10 shown in FIG.
Is a dielectric substrate 1 made of a dielectric material such as ceramics.
1 has electrodes 12 and 13 formed on both main surfaces.
In the capacitor 10, the bonding wire 14 is often bonded to the upper electrode 12 and the lower electrode 13 is often die-bonded to an electrode land or the like.

[0004]

In the multilayer capacitor 1 shown in FIG. 2, since the external electrodes 7, 8 are formed by applying and baking a conductive paste, the surfaces of the external electrodes 7, 8 are rounded. It is usually carried. Therefore, as shown in an enlarged view in FIG. 4, for example, when the bonding wire 9a is bonded to the external electrode 7, the bonding wire 9a cannot be reliably bonded to the external electrode 7, and a bonding failure often occurs. was there.

[0005] Further, in performing the above-described wire bonding, it is essential to apply a flux to the external electrodes 7 and 8 at the time of bonding in order to reduce the frequency of mounting failure as much as possible. However, the IC chip itself is usually made of a material that is corroded by the flux. Therefore, in a structure such as a hybrid IC in which an IC chip and a capacitor are built in an IC package, after the multilayer capacitor 1 is attached,
The complicated work of cleaning the flux had to be performed.

On the other hand, the single-plate type capacitor 1 shown in FIG.
In the case of 0, the flatness of the electrodes 12 and 13 is ensured, so that the bonding wire 14 can be securely bonded. However, in the single-plate capacitor 10,
There is a problem that it is difficult to obtain a high capacity.

Further, since the capacitance is closely related to the thickness of the dielectric substrate 11, there is a disadvantage that the tolerance of the thickness of the capacitor 10 is small. In general, when performing wire bonding, if the thickness of each component to be bonded is not uniform, there is a tendency that poor bonding is likely to occur. Therefore, it is required that the thickness of each component be uniform in the above-mentioned applications.
0, if the thickness is adjusted to the thickness of another component such as an IC chip, the electrodes 12 and 13 are required to obtain a desired capacitance.
Must be greatly changed. Therefore, the space for mounting the capacitor may be changed or may not be accommodated in the IC package.

Therefore, an object of the present invention is to make it possible to reliably and easily perform bonding at an external electrode, to keep the thickness constant even when the capacitance is changed, and to easily increase the capacitance. It is to provide a simple multilayer capacitor.

[0009]

Means for Solving the Problems The present invention relates to ceramics.
Ceramic sintered body obtained by integrally firing
Was a multi-layer capacitor, block-shaped ceramic
A dielectric chip made of a sintered body , and arranged in a direction orthogonal to a pair of opposed outer surfaces having the largest area of the dielectric chip so as to overlap with each other via a dielectric layer in the dielectric chip. A plurality of internal electrodes having a rectangular shape; and a pair of outer surfaces having the largest area of the dielectric chip, which are formed on a pair of opposing outer surfaces, respectively. first, second and an external electrode, wherein one side of the long sides of the internal electrode dielectric chip and to electrically connect, connected to predetermined internal electrodes of the plurality of internal electrodes in large opposing surfaces of the largest area of the first or second
And the other side of the internal electrode is connected to
Embedded in the dielectric chip, and has the largest area
Characterized in that one of the opposing surfaces is a surface to be attached to a substrate . Claims
In the invention described in 2, the opposing surface having the largest area is provided.
Inside, opposite to the opposite surface that is the mounting surface to the board
External electrodes formed on the opposite surface of the
Is configured to be electrically connected to the inside by
I have.

[0010]

In the multilayer capacitor of the present invention, the first and second external electrodes are formed on at least one of a pair of opposed outer surfaces of the dielectric chip having the largest area. Therefore, since the planarity of the first and second external electrodes is enhanced, bonding by the bonding wire can be performed reliably and easily.

Further, a plurality of internal electrodes having a rectangular shape, Ri Contact disposed within the dielectric chip so as to extend in a direction perpendicular to the pair of outer surfaces opposite to each other of the largest area, rectangular shape sides of the long sides of the internal electrodes having found what is connected to the first or second external electrode Oite one <br/> large opposing surfaces of the largest area of the dielectric chip
Thus, the reliability of the electrical connection between the internal electrode and the external electrode can be improved, and the inductance can be reduced . In addition, the other side of the internal electrode is embedded in the dielectric chip.
Since it is provided, the moisture resistance is also good. In addition, multiple
Internal electrodes are arranged in a direction perpendicular to the mounting surface.
Runode, even if the increased number of lamination of the plurality of internal electrodes, the distance between the pair of outer surfaces of large opposing the most area of the dielectric chip may be a constant. That is, even when the number of stacked layers is increased to achieve a higher capacity, or when the number of stacked layers is reduced to reduce the capacity, a pair of opposing outer surfaces having the largest area are opposed to each other. Can be constant. According to the invention of claim 2, a pair of opposing outer surfaces is provided.
Of the external electrodes formed on the surface opposite to the mounting surface
Connect so that it is connected to the outside by the bonding wire.
Has been continued. Therefore, in the multilayer capacitor according to the present invention,
When mounted on the circuit board,
The external electrode and the outside are connected by a short bonding wire.
Remaining due to the bonding wire.
The remaining inductance can be reduced.

Therefore, if the pair of outer surfaces having the largest area and facing each other is used as an upper surface or a lower surface so as to be mounted in an IC package, it is easy to make the thickness of other components such as an IC chip uniform. . Therefore, it is possible to effectively prevent the occurrence of bonding failure due to wire bonding.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer capacitor according to an embodiment of the present invention will be described with reference to FIGS. The multilayer capacitor 21 is configured using a rectangular parallelepiped dielectric chip 22. In this embodiment, the dielectric chip 22 is formed of a ceramic sintered body obtained by integrally firing dielectric ceramics with an internal electrode described later. However, the dielectric chip 22 may be made of a dielectric material other than ceramics, for example, a synthetic resin. Also,
The shape of the dielectric chip 22 is not limited to the illustrated rectangular parallelepiped shape as long as it is a block shape, and may be, for example, a cubic shape.

As is clear from FIGS. 1 (a) and 1 (b),
In the dielectric chip 22, a plurality of internal electrodes 23a to 23
j are arranged so as to face each other via the dielectric layer.
Of these, the internal electrodes 23a, 23c, 23e, 23g,
23 i is drawn out to the upper surface 22 a of the dielectric chip 22. On the other hand, the internal electrodes 23b, 23d, 23f, 23
h and 23j are extended to the lower surface 22b of the dielectric chip 22. In the present embodiment, the upper surface 22a and the lower surface 22b
Constitute the outer surface having the largest area among the outer surfaces of the dielectric chip 22. Therefore, the plurality of internal electrodes 23
a to 23j are the upper surface 22 which is the outer surface of the largest area.
a and the lower surface 22b.

The dielectric chip 22 is formed by laminating a plurality of ceramic green sheets coated with a conductive paste for forming the plurality of internal electrodes 23a to 23j, and further printing a conductive paste on the outside as necessary. It is obtained by laminating a suitable number of ceramic green sheets, pressing them in the thickness direction, and firing.

On the upper surface 22a of the dielectric chip 22, a first
Of the second external electrode 2 on the lower surface 22b.
5 are formed. The external electrodes 24 and 25 can be formed by an appropriate method such as application and baking of a conductive paste, sputtering, vapor deposition or plating.
In order to improve the flatness of the layers 4 and 25, it is preferable to form them by a thin film forming method such as sputtering or vapor deposition. As a metal material for forming the external electrodes 24 and 25, T
An appropriate metal such as i, Ni, Ag, Au, or a Ni—Cr alloy can be used.

In the multilayer capacitor 21 of this embodiment, the upper surface 22 which is the outer surface of the dielectric chip 22 having the largest area
External electrodes 24 and 25 are formed on the lower surface 22a and the lower surface 22b. Therefore, the flatness of the external electrodes 24 and 25 is the same as that of FIG.
Since the flatness of the external electrodes 7 and 8 of the multilayer capacitor 1 shown in FIG. 1 is increased, bonding by bonding wires can be performed reliably and easily.

The capacitance of the multilayer capacitor 21 can be adjusted by changing the number and area of the internal electrodes 23a to 23j. In this case, the distance between the upper surface 22a and the lower surface 22b is changed. The capacity can be changed without the need. Accordingly, as shown in FIG. 6, when the dielectric chip 22 is mounted in the IC package 26 so that the upper surface 22a of the dielectric chip 22 is located below, the thickness of the IC chip 27 and other components can be easily adjusted. That is, even when the thickness of the IC chip 27 is made equal to that of the IC chip 27, multilayer capacitors having various capacities can be formed. Therefore, when used as a capacitor incorporated in an IC package as shown in FIG. 6, bonding by the bonding wire 28 in the IC package 26 can be reliably performed.

The multilayer capacitor 21 has the number of stacked internal electrodes 23a to 23j and the internal electrodes 23a to 23j.
By changing the thickness of the dielectric layer sandwiched between 3j, miniaturization and high capacity can be easily achieved. Therefore, by using the multilayer capacitor 21, the mounting density can be increased. Further, since the external electrodes 24 and 25 having excellent flatness are formed on the upper surface 22a and the lower surface 22b of the dielectric chip 22 as described above, wire bonding can be performed easily and reliably.
It is possible to connect to other parts by the bonding wire 28 without using a flux. Therefore,
It is possible to omit a complicated washing operation as in the case of using a flux.

In addition, when the external electrodes 24 and 25 are stacked on the upper and lower surfaces, a plurality of internal electrodes 2
Since 3a to 23j are arranged in a direction orthogonal to the circuit board, the inductance component can be reduced, and the frequency characteristics at the time of mounting can be improved.

[0021]

[0022]

[0023]

When mounting the multilayer capacitor 31 on a circuit board, as shown in FIG. 7 , the lower surface 32a of the dielectric chip 32 can be fixed on the circuit board 40 by bonding with an insulating adhesive 41. it can. In this case,
The electrical connection with other components is made by, for example, the external electrodes 34 and 3
5 may be bonded to the bonding wires 42 and 43.

As shown in FIG. 8 , first and second external electrodes 34 and 35 are die-bonded to electrode lands 45 and 46 formed on a circuit board 41 to form first and second external electrodes. External electrodes 34 and 35 are connected to electrode lands 45 and 4.
6 can also be electrically connected. Further, a bump electrode may be formed on a circuit board, and the first and second external electrodes 34 and 35 may be joined to the bump electrode.

In the multilayer capacitors 21 and 31 of the first and second embodiments, the first and second external electrodes 24 and 2 are provided.
Since the flatness of 5, 34, 35 is enhanced, wire bonding can be performed easily and reliably.
The external electrodes 24, 2 are formed by a thin film forming method such as vapor deposition and sputtering.
When 5, 34, and 35 are formed, the flatness is further increased, so that the bonding failure of wire bonding can be more effectively prevented. In addition, if the first and second external electrodes are formed by the thin film forming method, the space required for the solder fillet required when the external electrodes composed of the thick film electrodes are joined by soldering can be omitted. Becomes Therefore, it is possible to further increase the mounting density.

[0027]

[Effect of the Invention] In the present invention, the first and second external electrodes are
Since it is formed on at least one of the outer surfaces of the dielectric chip having the largest area, the first and second external electrodes are formed so as to have sufficient planarity. Therefore, it is possible to effectively enhance the reliability of bonding by a bonding wire, and to perform bonding without using a flux. Therefore, it is possible to provide a multilayer capacitor suitable for a device or a circuit that cannot use a flux. it can.
Also, the internal electrodes are arranged so as to be orthogonal to the mounting surface.
Therefore, when the number of laminated internal electrodes is increased or decreased,
The distance between the opposing surfaces with the largest area must be constant.
Can be. Further, the internal electrode has a rectangular shape,
Since one side of the long side of the internal electrode is connected to the first or second external electrode in large opposing surfaces of the largest area of the dielectric chip, the reliability of connection between the external electrode and the internal electrode enhances together is, Ru can achieve low inductance. The other side of the internal electrode is inside the dielectric chip.
Since it is buried in, the moisture resistance is also improved. Claim 2
In the invention described in, one of the opposing surfaces with the largest area is
A mounting surface, and a direction orthogonal to the mounting surface
The above multiple internal electrodes are arranged in
The external electrode formed on the opposite surface opposite to the
To be electrically connected by bonding wires
It is configured. Therefore, the multilayer capacitor according to the present invention
Bonding on the circuit board etc.
One external electrode is electrically connected to the outside by a wire.
The length of the bonding wire
Can also reduce inductance
it can. Therefore, a low-inductance capacitor suitable as an IC chip capacitor can be provided.

Further, in the multilayer capacitor of the present invention, since the capacitance can be changed without changing the distance between the outer surfaces having the largest area, the distance between the outer surfaces having the largest area is kept constant. The thickness can be made uniform with other components such as an IC chip and the like, so that a defect at the time of wire bonding attachment can be prevented. In addition, since a plurality of internal electrodes are stacked via a dielectric layer, it is possible to achieve high capacity and miniaturization.

[Brief description of the drawings]

1A is a cross-sectional view of a multilayer capacitor according to an embodiment of the present invention, and is a cross-sectional view taken along line AA of FIG. 5, and FIG. 1B is a cross-sectional view taken along line BB of FIG. .

FIG. 2 is a sectional view showing an example of a conventional multilayer capacitor.

FIG. 3 is a sectional view showing a conventional single-plate type capacitor.

FIG. 4 is a partially enlarged cross-sectional view for explaining a problem of the conventional multilayer capacitor.

FIG. 5 is a perspective view of the multilayer capacitor according to the embodiment of the present invention;

FIG. 6 is a partially cutaway sectional view showing an IC package configured using the multilayer capacitor according to one embodiment of the present invention;

FIG. 7 shows an example of a method of using a multilayer capacitor according to another embodiment .
FIG.

FIG. 8 shows another method of using the multilayer capacitor of another embodiment .
Sectional drawing for demonstrating an example.

[Explanation of symbols]

 Reference Signs List 21 multilayer capacitor 22 dielectric chip 22a upper surface as outer surface having the largest area 22b lower surface as outer surface having the largest area 23a to 23j internal electrode 24 first external electrode 25 second external electrode

Claims (2)

(57) [Scope of request for utility model registration] 1. A ceramic and an internal electrode are integrally fired.
A multilayer capacitor using a ceramic sintered body
A dielectric chip made of a block-shaped ceramic sintered body , and orthogonal to a pair of opposing outer surfaces having the largest area of the dielectric chip so as to overlap with each other via a dielectric layer in the dielectric chip. And a plurality of internal electrodes having a rectangular shape, respectively formed on a pair of opposing outer surfaces having the largest area of the dielectric chip, and between the plurality of internal electrodes. to connect the capacitor to be taken to the outside electrically, the first connected to predetermined internal electrodes of the plurality of internal electrodes, and a second external electrodes, one long side of the inner electrode The side is connected to the first or second external electrode on the opposing surface of the dielectric chip having the largest area, and the other side of the internal electrode is connected to the dielectric chip.
Is embedded within, Installing to one is the substrate of the large opposing surfaces of the largest area
A multilayer capacitor, characterized in that the capacitor has a surface . 2. A base of the opposed surface having the largest area.
Opposite surface opposite to the surface to be attached to the plate
External electrodes formed on the facing surface
It is configured to be more electrically connected to the inside,
The multilayer capacitor according to claim 1.