JP4906990B2 - Through-type multilayer ceramic capacitors for three-dimensional mounting - Google Patents

Through-type multilayer ceramic capacitors for three-dimensional mounting Download PDF

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Publication number
JP4906990B2
JP4906990B2 JP33757999A JP33757999A JP4906990B2 JP 4906990 B2 JP4906990 B2 JP 4906990B2 JP 33757999 A JP33757999 A JP 33757999A JP 33757999 A JP33757999 A JP 33757999A JP 4906990 B2 JP4906990 B2 JP 4906990B2
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Prior art keywords
chip body
ceramic layer
multilayer
internal electrodes
electrodes
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JP2001155954A (en
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泰介 安彦
正明 富樫
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TDK Corp
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TDK Corp
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Description

【0001】
【発明の属する技術分野】
本発明は、低ESLで、且つ、低ESRなコンデンサとしてパソコン等の動作周波数が高速化する電子機器搭載用に好適で、電子機器の小型化から高さ方向を低く保って三次元の多層プリント基板等に表面実装するのに適する三次元搭載用の貫通型積層セラミックコンデンサに関するものである。
【0002】
【従来の技術】
一般に、パソコン等の電子機器においては動作周波数が500MHzから1GHzへと高速化が進んでおり、その電源回路には低ESLで、且つ、低ESRな積層セラミックコンデンサが必要とされている。また、電子機器の小型化から高さ方向を低く抑えて三次元のプリント基板等に確実に表面実装可能で所定の特性も得られる積層セラミックコンデンサが要請されている。
【0003】
従来、貫通型の積層セラミックコンデンサにおいては、図5で示すように内部電極10…、10a,10b…としてセラミック層11…を隔て交差する方向に位置する二つの異なる電極パターンのものを交互に複数積層形成した積層チップ素体を部品本体に構成するものが知られている(特公昭62−35257号)。
【0004】
その内部電極のうち、一つはセラミック層11…の中間辺で両辺の間に亘る一本の内部電極10…とし、他の一つは一本の内部電極10…と直交する方向でセラミック層11…の他の辺間に亘る少なくとも二本の平行した内部電極10a,10b…として形成されている。
【0005】
その積層チップ素体によっては、図6で示すように各内部電極10、10a,10b…とセラミック層11…の積層面に露出する部分で電気的に導通する外部電極12a,12b、13a,13b…(片側のみ図示)を積層チップ素体の側端面に設けることにより貫通型の積層セラミックコンデンサとして構成されている。
【0006】
その積層セラミックコンデンサは、各外部電極12a,12b、13a,13b…を回路基板14の板面より直立方向に位置させて部品全体を回路基板15の板面上に載置し、外部電極12a,12b、13a,13b…の側面と回路パターン15a,15b、16a,16b…のランド部とを半田盛り17…で接合固定することにより表面実装されている。
【0007】
その積層セラミックコンデンサを長方形のセラミック層で構成すると、内部電極の相対するいずれかがセラミック層の短辺間に亘って細長く延び、この外部電極の相対する距離が長くなることによりインダクタンス成分が大きくなる。これと共に、外部電極の間隔が長いため、回路基板に形成する回路パターンが長くなり、ランド部の引回しが長くなってインダクタンス成分に影響を与える。
【0008】
特に、三次元の多層プリント基板等に表面実装すると、上部位置のランド部と下部位置のランド部とで構成される回路パターンが長くなり、ランド部の引回しが長くなってインダクタンス成分に影響を与えることとなり、ノイズの発生を避けられない。また、ESLを低くし、例えば、半導体等の端子近傍に表面実装搭載すると、三次元のプリント基板等に実装時におけるランド部の引回しによるインダクタンス成分の影響を無視できない。
【0009】
それ以外に、部品全体の高さ方向が各層の積層方向に相当するため、各層の積層数如何によって部品全体の高さ方向を低く抑えられないところから、三次元搭載用の貫通型積層セラミックコンデンサとして適さない。
【0010】
【発明が解決しようとする課題】
本発明は、外部電極の間隔を狭くすることにより低ESLで、且つ、低ESRなコンデンサとしてパソコン等の動作周波数が高速化する電子機器搭載用に好適で、電子機器の小型化から部品全体の高さ方向を低く抑えて三次元の多層プリント基板等に表面実装するのに好適な三次元搭載用貫通型積層セラミックコンデンサを提供することを目的とする。
【0011】
【課題を解決するための手段】
本発明に係る三次元搭載用貫通型積層セラミックコンデンサにおいては、セラミック層を介し、セラミック層の各短辺寄りを除く中間部で両長辺に亘る第1の内部電極と、セラミック層の面内に位置する主要部から各短辺に延びる二つの引出し部を有する第2の内部電極とを交互に積層させて積層チップ素体を形成し、
第1の内部電極とセラミック層の各長辺に露出する部分で電気的に導通する外部電極を積層チップ素体の相対する上下面に設け、第2の内部電極と各引出し部で電気的に導通する外部電極を積層チップ素体の側端面全周に亘って設け、
その積層チップ素体を形成するセラミック層の短辺側を高さ方向として部品全体の高さ方向を低く抑え部品全体を上下の相対する回路基板の板面間に挟みこむと共に部品全体の側端面を高さ方向で別の回路基板の板面に埋め込み、各外部電極を回路基板の異なる回路パターンと各々直に対面させて電気的に接合する三次元搭載用の貫通型として構成されている。
【0012】
【発明の実施の形態】
以下、図1〜図4を参照して説明すると、図示実施に形態に係る三次元搭載用の貫通型積層セラミックコンデンサは、図1で示すように所定パターンの内部電極1,1…と長方形のセラミック層2…とを交互に複数積層させて積層チップ素体を形成し、その積層チップ素体の内部電極1,1…と電気的に導通する外部電極3、4を積層チップ素体の所定面に設けることにより構成されている。
【0013】
内部電極1,1…は、Ni等の導電性ペーストをセラミックグリーンシートのシート面に塗布,焼付処理することによりNi若しくはNi合金層等で形成し、また、卑金属のCu,貴金属のPd若しくはPd−Ag合金層等でも形成できる。セラミック層2…は、チタン酸バリウム系,チタン系,ジルコン酸系等のセラミック材料を主成分とするセラミックペーストをベースフィルムのフィルム面上に塗布してから焼成,燒結処理することにより形成する。
【0014】
その内部電極1,1…は、図2で示すように第1の内部電極1…としてセラミック層2…の各短辺2a,2b寄りを除く中間部で両長辺2c,2dに亘る電極パターンのものと、第2の内部電極1…としてセラミック層の面内に位置する主要部1aから各短辺2a,2bに延びる二つの引出し部1b,1cを有する電極パターンのものとから形成されている。なお、第2の内部電極1…の引出し部1b,1cは主要部1aと同じ幅に形成してもよい。
【0015】
その内部電極1,1…と長方形のセラミック層2…とを交互に複数積層させて積層チップ素体を形成し、更には内部電極を設けないセラミック層2を最外層の保護層として積層することにより積層チップ素体を構成できる。
【0016】
その積層チップ素体を部品本体とし、セラミック層2…の短辺2a,2bに相当する側を部品全体の高さ方向H、セラミック層2…の短辺2a,2bで形成する積層面を側端面、セラミック層2…の長辺2c,2dで形成する積層面を上下面とし、第1の内部電極1…とセラミック層2の長辺2c,2dに沿って露出する部分で電気的に導通する各外部電極3(作図上、下側は隠れている。)を積層チップ素体の上下面に設けると共に、第2の内部電極1…と主要部1aからセラミック層2の各短辺2a,2bに延びる二つの引出し部1b,1cで電気的に導通する外部電極4(作図上、背面側は隠れている。)を積層チップ素体の側端面全周に亘って設ける。
【0017】
その外部電極3、4はCuペーストを塗布,乾燥することにより下地層とし、Ni及びSnのメッキ層を下地層に被着することにより形成できる。この外部電極3、4によっては、回路基板の異なる回路パターンと各々直に対面させて電気的に接合する三次元搭載用の貫通型積層セラミックコンデンサとして構成されている。
【0018】
その外部電極3,4のうち、第1の内部電極1…と電気的に導通する外部電極3はセラミック層2…の長辺2c,2で形成する積層チップ素体の積層面全面に形成できる。また、多層基板のランド形状により外部電極3の広さを設定するところから、外部電極3はセラミック層2…の長辺2c,2dで形成する積層チップ素体の積層面における少なくとも50%以上の面積を保つことによっても形成できる。
【0019】
その具体例としては、部品全体の寸法を高さ0.5±0.1mm、幅0.8±0.1mm、長さ1.6±0.1mmの大きさに構成できる。セラミック層一層分としては厚み4μmで、形状的には短辺0.5±0.1mm、長辺0.8±0.1mmの大きさに形成できる。外部電極3と相対する外部電極との間隔は、セラミック層の短辺に相当する長さに設定できる。
【0020】
このように構成する貫通型の積層セラミックコンデンサCは、図4で示すような半導体装置Dを備える電源回路において上下の相対する回路基板5,6の板面間に挟み込むよう組付け搭載できる。その三次元搭載は、上下の相対する外部電極3,3’を回路基板5,6の異なる回路パターン7a,7bと各々直に対面させ、また、側端面全周に亘る外部端子4を別の回路基板に設けた回路パターン8a,8bと各々直に対面させて+極/―極(GND)として電気的に接合することにより行える。この三次元搭載では、部品全体の高さ方向Hを低く抑えられしかも回路基板5,6の相対間隔を狭く保てることにより、ランド部の引回しが長くなることによるインダクタンス成分の影響を少なくできる。
【0021】
その回路パターンのインダクタンスを低減させるに、ESL値は10〜20pH、ESR値は5〜7mΩと低い積層セラミックコンデンサCを回路基板(図示せず)の板面に埋め込むことから、ランド部のインダクタンス成分を無視できる。これにより、従来例に係る静電容量値が0.22μFの積層セラミックコンデンサと、本発明に係る積層セラミックコンデンサ(従来例と同じ静電容量値)とのESL及びESRを比較すると、従来に係る積層セラミックコンデンサを100%とすると、本発明に係る積層セラミックコンデンサは2〜3%と低くできた。
【0022】
それは、本発明に係る貫通型積層セラミックコンデンサでは外部電極3、4の間隔が短く、部品全体の高さ方向を低く抑えられ、また、外部電極3、が幅広で表面実装し易いため、多層基板に搭載しても、ランド部の引回しによるトータルインダクタンスを少なくできて多層基板に形成するランドも簡素化できることによる。
【0023】
【発明の効果】
以上の如く、本発明に係る三次元搭載用貫通型積層セラミックコンデンサに依れば、積層チップ素体を形成するセラミック層の短辺側を高さ方向として部品全体の高さ方向を低く抑え部品全体を上下の相対する回路基板の板面間に挟み込むと共に部品全体の側端面を高さ方向で別の回路基板の板面に埋め込み、各外部電極を回路基板の異なる回路パターンと各々直に対面させて電気的に接合する三次元搭載用の貫通型として構成することにより、外部電極の間隔を短くしかも部品全体の高さ方向を低く抑えられるため、多層基板に搭載しても、ランド部の引回しによるトータルインダクタンスを少なくできて多層基板に形成するランドも簡素化でき、低ESLで、且つ、低ESRなコンデンサとしてパソコン等の動作周波数が高速化する電子機器搭載用に好適で、電子機器の小型化から部品全体の高さ方向を低く抑えて三次元の多層プリント基板等に表面実装するのに好適なものとして構成することができる。
【図面の簡単な説明】
【図1】本発明に係る三次元搭載用貫通型積層セラミックコンデンサを内部構造の透視状態で示す斜視図である。
【図2】本発明に係る三次元搭載用貫通型積層セラミックコンデンサを構成する内部電極のパターン形状を示す説明図である。
【図3】本発明に係る三次元搭載用貫通型積層セラミックコンデンサの外部電極を含む外観を示す斜視図である。
【図4】本発明に係る三次元搭載用貫通型積層セラミックコンデンサの多層基板における挟込み搭載構造を示す説明図である。
【図5】従来例に係る貫通型積層セラミックコンデンサを構成する内部電極のパターン形状を示す説明図である。
【図6】従来例に係る三次元搭載用貫通型積層セラミックコンデンサの実装構造を示す説明図である。
【符号の説明】
C 三次元搭載用貫通型積層セラミックコンデンサ
… 第1の内部電極
… 第2の内部電極
1a 第2の内部電極の主要部
1b,1c 第2の内部電極の引出し部
2… セラミック層
2a,2b セラミック層の短辺
2c,2d セラミック層の長辺
3、4 外部電極
5、6 回路基板
7a,7b、8a,8b 回路パターン
H 部品全体の高さ方向
[0001]
BACKGROUND OF THE INVENTION
The present invention is a low ESL and low ESR capacitor suitable for mounting on an electronic device such as a personal computer that has a high operating frequency, and is capable of three-dimensional multilayer printing by keeping the height direction low from the downsizing of the electronic device. The present invention relates to a feedthrough multilayer ceramic capacitor for three-dimensional mounting suitable for surface mounting on a substrate or the like.
[0002]
[Prior art]
In general, in electronic devices such as personal computers, the operating frequency has been increased from 500 MHz to 1 GHz, and a multilayer ceramic capacitor with low ESL and low ESR is required for its power supply circuit. In addition, there has been a demand for a multilayer ceramic capacitor that can be mounted on a three-dimensional printed circuit board or the like with a reduced height in an electronic device, and that can be reliably surface-mounted and have predetermined characteristics.
[0003]
Conventionally, in a through-type multilayer ceramic capacitor, as shown in FIG. 5, a plurality of alternating electrodes having two different electrode patterns positioned in a direction crossing the ceramic layer 11 as the internal electrodes 10... 10a, 10b. There is known a structure in which a laminated chip body is formed in a component body (Japanese Patent Publication No. 62-35257).
[0004]
Among the internal electrodes, one is an inner side of the ceramic layer 11 and one internal electrode 10 extending between the two sides, and the other is a ceramic layer in a direction perpendicular to the single internal electrode 10. Are formed as at least two parallel internal electrodes 10a, 10b... Extending between the other sides.
[0005]
Depending on the laminated chip body, as shown in FIG. 6, external electrodes 12a, 12b, 13a, 13b that are electrically conductive at portions exposed to the laminated surface of the internal electrodes 10, 10a, 10b,. ... (only one side is shown) is provided on the side end face of the multilayer chip body to constitute a through-type multilayer ceramic capacitor.
[0006]
In the multilayer ceramic capacitor, the external electrodes 12a, 12b, 13a, 13b... Are positioned in an upright direction from the plate surface of the circuit board 14, and the entire component is placed on the plate surface of the circuit board 15, and the external electrodes 12a, 12a, The surface mounting is performed by joining and fixing the side surfaces of 12b, 13a, 13b... And the land portions of the circuit patterns 15a, 15b, 16a, 16b.
[0007]
When the multilayer ceramic capacitor is formed of a rectangular ceramic layer, any of the internal electrodes facing each other extends elongated between the short sides of the ceramic layer, and the distance between the external electrodes increases to increase the inductance component. . At the same time, since the distance between the external electrodes is long, the circuit pattern formed on the circuit board becomes long, and the routing of the land portion becomes long, affecting the inductance component.
[0008]
In particular, when surface-mounted on a three-dimensional multilayer printed circuit board, etc., the circuit pattern composed of the land portion at the upper position and the land portion at the lower position becomes longer, and the routing of the land portion becomes longer, affecting the inductance component. The generation of noise is inevitable. Further, when the ESL is lowered and, for example, mounted on the surface in the vicinity of a terminal such as a semiconductor, the influence of the inductance component due to the routing of the land portion when mounted on a three-dimensional printed circuit board cannot be ignored.
[0009]
In addition, since the height direction of the entire component corresponds to the stacking direction of each layer, the height direction of the entire component cannot be kept low depending on the number of layers in each layer. Not suitable as.
[0010]
[Problems to be solved by the invention]
The present invention is suitable for mounting on an electronic device in which the operating frequency of a personal computer or the like is increased as a low ESL and low ESR capacitor by narrowing the interval between the external electrodes. It is an object of the present invention to provide a three-dimensional mounting through-type multilayer ceramic capacitor suitable for surface mounting on a three-dimensional multilayer printed circuit board or the like while keeping the height direction low.
[0011]
[Means for Solving the Problems]
In the through-type multilayer ceramic capacitor for three-dimensional mounting according to the present invention, the first internal electrode extending over both long sides in the middle portion excluding the short sides of the ceramic layer via the ceramic layer, and the in-plane of the ceramic layer Forming a laminated chip body by alternately laminating the second internal electrodes having two lead portions extending from the main portion located on the short side to each short side,
External electrodes that are electrically connected to the first internal electrodes and the exposed portions of the long sides of the ceramic layer are provided on the upper and lower surfaces of the multilayer chip body, and the second internal electrodes and the lead portions are electrically connected to each other. Conductive external electrodes are provided over the entire circumference of the side end surface of the multilayer chip body,
The short side of the ceramic layer to form the laminated chip element and the height direction suppressing the height direction of the whole parts, with sandwich the entire part between the plate surfaces of the upper and lower opposing circuit board, the entire component 3D mounting through type that embeds the side end face of the circuit board in the height direction on the surface of another circuit board and electrically connects each external electrode directly to the different circuit pattern of each circuit board Has been.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
1 to 4, the through-type multilayer ceramic capacitor for three-dimensional mounting according to the illustrated embodiment includes internal electrodes 1 1 , 1 2 ... Having a predetermined pattern as shown in FIG. A plurality of rectangular ceramic layers 2 are alternately stacked to form a multilayer chip body, and external electrodes 3 and 4 electrically connected to the internal electrodes 1 1 , 1 2 ... Of the multilayer chip body are stacked chips. It is configured by being provided on a predetermined surface of the element body.
[0013]
The internal electrodes 1 1 , 1 2 ... Are formed of a Ni or Ni alloy layer by applying and baking a conductive paste such as Ni on the sheet surface of the ceramic green sheet. Alternatively, a Pd—Ag alloy layer can be formed. The ceramic layers 2 are formed by applying a ceramic paste mainly composed of a barium titanate-based, titanium-based, or zirconic acid-based ceramic material on the film surface of the base film, followed by firing and sintering.
[0014]
As shown in FIG. 2, the internal electrodes 1 1 , 1 2 ... Are formed as first internal electrodes 1 1 ... On the long sides 2 c and 2 d at the intermediate portion except for the short sides 2 a and 2 b of the ceramic layer 2. And an electrode pattern having two lead portions 1b and 1c extending from the main portion 1a located in the plane of the ceramic layer to the short sides 2a and 2b as the second internal electrodes 1 2 . Formed from. The lead portions 1b and 1c of the second internal electrodes 1 2 ... May be formed to have the same width as the main portion 1a.
[0015]
A plurality of internal electrodes 1 1 , 1 2 ... And rectangular ceramic layers 2... Are alternately stacked to form a multilayer chip body, and further, a ceramic layer 2 without internal electrodes is stacked as the outermost protective layer. By doing so, a laminated chip body can be configured.
[0016]
The laminated chip body is used as a component body, and the side corresponding to the short sides 2a and 2b of the ceramic layer 2 is formed in the height direction H of the entire component, and the laminated surface formed by the short sides 2a and 2b of the ceramic layer 2 is disposed on the side. The end surface, the laminated surface formed by the long sides 2c and 2d of the ceramic layer 2 is defined as the upper and lower surfaces, and the first inner electrodes 1 1 and the portions exposed along the long sides 2c and 2d of the ceramic layer 2 are electrically connected. Each conductive external electrode 3 (the lower side is hidden in the drawing) is provided on the upper and lower surfaces of the multilayer chip body, and each short side of the ceramic layer 2 from the second internal electrode 1 2 . External electrodes 4 (on the drawing, the rear side is hidden) that are electrically connected by the two lead portions 1b and 1c extending to 2a and 2b are provided over the entire circumference of the side end surface of the multilayer chip body.
[0017]
The external electrodes 3 and 4 can be formed by applying a Cu paste and drying to form a base layer, and depositing a Ni and Sn plating layer on the base layer. Each of the external electrodes 3 and 4 is configured as a three-dimensional mounting through-type multilayer ceramic capacitor that directly faces and electrically joins different circuit patterns on the circuit board.
[0018]
Of the external electrodes 3 and 4, the external electrode 3 electrically connected to the first internal electrodes 1 1 ... Is formed on the entire laminated surface of the laminated chip body formed by the long sides 2 c and 2 d of the ceramic layers 2. Can be formed. Further, since the width of the external electrode 3 is set according to the land shape of the multilayer substrate, the external electrode 3 is at least 50% or more on the laminated surface of the laminated chip body formed by the long sides 2c and 2d of the ceramic layers 2. It can also be formed by keeping the area.
[0019]
As a specific example, the dimensions of the entire part can be configured to be 0.5 ± 0.1 mm in height, 0.8 ± 0.1 mm in width, and 1.6 ± 0.1 mm in length. The ceramic layer has a thickness of 4 μm and can be formed in a shape having a short side of 0.5 ± 0.1 mm and a long side of 0.8 ± 0.1 mm. The distance between the external electrode 3 and the opposing external electrode can be set to a length corresponding to the short side of the ceramic layer.
[0020]
The through-type multilayer ceramic capacitor C configured as described above can be assembled and mounted so as to be sandwiched between the upper and lower opposed circuit boards 5 and 6 in the power supply circuit including the semiconductor device D as shown in FIG. In the three-dimensional mounting, the upper and lower external electrodes 3 and 3 ′ are directly opposed to different circuit patterns 7 a and 7 b on the circuit boards 5 and 6, and the external terminals 4 over the entire circumference of the side end surface are separated. The circuit patterns 8a and 8b provided on the circuit board can be directly faced to each other and electrically joined as + pole / -pole (GND). In this three-dimensional mounting, the height direction H of the entire component can be kept low, and the relative distance between the circuit boards 5 and 6 can be kept small, so that the influence of the inductance component due to the long routing of the land portion can be reduced.
[0021]
In order to reduce the inductance of the circuit pattern, a multilayer ceramic capacitor C having an ESL value of 10 to 20 pH and an ESR value of 5 to 7 mΩ is embedded in the plate surface of a circuit board (not shown). Can be ignored. As a result, when the ESL and ESR of the multilayer ceramic capacitor having the capacitance value of 0.22 μF according to the conventional example and the multilayer ceramic capacitor according to the present invention (the same capacitance value as the conventional example) are compared, When the multilayer ceramic capacitor is 100%, the multilayer ceramic capacitor according to the present invention can be as low as 2-3%.
[0022]
In the through-type multilayer ceramic capacitor according to the present invention, the interval between the external electrodes 3 and 4 is short, the height direction of the entire component can be kept low, and the external electrodes 3 and 4 are wide and easy to be surface-mounted. Even if it is mounted on the substrate, the total inductance due to the routing of the land portion can be reduced, and the land formed on the multilayer substrate can be simplified.
[0023]
【Effect of the invention】
As mentioned above, according to the three-dimensional mounting feedthrough multilayer ceramic capacitor according to the present invention, suppressing the height of the entire component to the short side of the ceramic layer to form a laminated chip element height direction The entire component is sandwiched between the upper and lower opposing circuit board plates , and the side end surfaces of the entire component are embedded in the plate surface of another circuit board in the height direction, and each external electrode has a different circuit pattern on each circuit board. By constructing as a three-dimensional mounting through type that directly faces each other and electrically joins, the distance between external electrodes can be shortened and the height direction of the entire component can be kept low. The total inductance due to the routing of the land can be reduced, the land formed on the multilayer substrate can be simplified, and the operating frequency of a personal computer or the like is increased as a low ESL and low ESR capacitor. Suitable electronics mounting, can be configured as suitable for surface mounting to suppress the reduction in size of electronic devices in the height direction of the entire component low three-dimensional multilayer printed circuit board or the like.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a three-dimensional mounting through-type multilayer ceramic capacitor according to the present invention in a transparent state of an internal structure.
FIG. 2 is an explanatory diagram showing a pattern shape of internal electrodes constituting the three-dimensional mounting through-type multilayer ceramic capacitor according to the present invention.
FIG. 3 is a perspective view showing an appearance including external electrodes of a three-dimensional mounting through-type multilayer ceramic capacitor according to the present invention.
FIG. 4 is an explanatory diagram showing a sandwich mounting structure in a multilayer substrate of a three-dimensional mounting through-type multilayer ceramic capacitor according to the present invention.
FIG. 5 is an explanatory view showing a pattern shape of internal electrodes constituting a through-type multilayer ceramic capacitor according to a conventional example.
FIG. 6 is an explanatory view showing a mounting structure of a three-dimensional mounting through-type multilayer ceramic capacitor according to a conventional example.
[Explanation of symbols]
C Three-dimensional mounting through-type multilayer ceramic capacitor 1 1 ... 1st internal electrode 1 2 ... 2nd internal electrode 1a Main part 1b of 2nd internal electrode, 1c Lead part 2 of 2nd internal electrode ... Ceramic layer 2a, 2b Ceramic layer short side 2c, 2d Ceramic layer long side 3, 4 External electrode 5, 6 Circuit boards 7a, 7b, 8a, 8b Circuit pattern H Height direction of entire component

Claims (1)

所定パターンの内部電極と長方形のセラミック層とを交互に複数積層させて積層チップ素体を形成し、その積層チップ素体の内部電極と電気的に導通する外部電極を積層チップ素体の所定面に設ける三次元搭載用の貫通型積層セラミックコンデンサにおいて、
セラミック層を介し、セラミック層の各短辺寄りを除く中間部で両長辺に亘る第1の内部電極と、セラミック層の面内に位置する主要部から各短辺に延びる二つの引出し部を有する第2の内部電極とを交互に積層させて積層チップ素体を形成し、
第1の内部電極とセラミック層の各長辺に露出する部分で電気的に導通する外部電極を積層チップ素体の相対する上下面に設け、第2の内部電極と各引出し部で電気的に導通する外部電極を積層チップ素体の側端面全周に亘って設け、
その積層チップ素体を形成するセラミック層の短辺側を高さ方向として部品全体の高さ方向を低く抑え部品全体を上下の相対する回路基板の板面間に挟み込むと共に部品全体の側端面を高さ方向で別の回路基板の板面に埋め込み、各外部電極を回路基板の異なる回路パターンと各々直に対面させて電気的に接合する三次元搭載用の貫通型として構成したことを特徴とする三次元搭載用貫通型積層セラミックコンデンサ。
A plurality of internal electrodes of a predetermined pattern and rectangular ceramic layers are alternately stacked to form a multilayer chip body, and external electrodes that are electrically connected to the internal electrodes of the multilayer chip body are connected to a predetermined surface of the multilayer chip body. In the through-type multilayer ceramic capacitor for three-dimensional mounting provided in
A first internal electrode extending over both long sides at the intermediate portion excluding the short sides of the ceramic layer through the ceramic layer, and two lead portions extending from the main portion located in the plane of the ceramic layer to the short sides. A laminated chip body is formed by alternately laminating second internal electrodes having
External electrodes that are electrically connected to the first internal electrodes and the exposed portions of the long sides of the ceramic layer are provided on the upper and lower surfaces of the multilayer chip body, and the second internal electrodes and the lead portions are electrically connected to each other. Conductive external electrodes are provided over the entire circumference of the side end surface of the multilayer chip body,
The short side of the ceramic layer to form the laminated chip element and the height direction suppressing the height direction of the whole parts, with sandwiching the entire part between the plate surfaces of the upper and lower opposing circuit board, the entire part of the The side end face is embedded in the board surface of another circuit board in the height direction, and each external electrode is configured as a through-type for three-dimensional mounting in which each circuit board directly faces each other and is electrically connected to each other. A three-dimensional through-type multilayer ceramic capacitor for mounting.
JP33757999A 1999-11-17 1999-11-29 Through-type multilayer ceramic capacitors for three-dimensional mounting Expired - Lifetime JP4906990B2 (en)

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